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(A" 6 AɃ6 Aʃ6  A: A˃ A˃AĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 Ȁ A6  Ȁ  (6A<" 6 Aˀ6 À6  A:: A AAĀ"6  ƀ A: AƁ р  ( JA" 6 Ã6 A̓6  A: A΃    Aj!@@@@@@@@@@ - ( !A" 6 A6 A6  6  A: A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  A! AH @ ( AqAF #AjA6  ( !A "A6 A6 B7  6  A: A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  A! AF @ AqE #AjA 6  @ AqAG #AjA6  ( !A("A:%  6 Aσ6 AЃ6  6  A:$ Aу AуAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 Ȁ A6 A΃ р Ȁ  VA(" 6 A҃6 AӃ6  6  6  A:$ Aԃ   ~@@@@@@@@ -$ ) ! (!A"A6$ Aր6 A׀6 B7  A AI6  7 A6  A: A؀ A؀AĀ"6 E   ƀ A:$  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 A`I A kA瀀 AҀAĀ"6  ƀ A:$  A!@@ ̀Aj ( ΀  (! ( #AjA k6 6 Ȁ A6 Aԃ р Ȁ  JA" 6 AՃ6 Aփ6  A: A׃   @@@@@@@@@ - A! ( "AH A" Aj6 A6 A6  6  A: A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  A!@@ AH ( AqAF #AjA6 (   (H"A AK"A AI"6A0" A0j6 A6 A6  A:, A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   A!A ( AAAAA"AjAK A!AA6AA k6  ( ! (! A6 B7 B7  6 A6  6 6 Ȁ A6 A׃ р Ȁ  HA" 6 Aʁ6 Aˁ6  A: A   @@@@@@@@ - @ ( "- #AjA6A!  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(A$" 6 Aǁ6 Aȁ6 A! A: AɁ AɁAĀ"6 E   ƀ A: ; @@ ̀Aj (΀  @@ ̀Aj (΀  ("(! A!   ((" A!  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(! @@  ( AqAG ) )R ) )Q  A!  (!A" Aj6 A6 A6  A: A AAĀ"6 E   ƀ A: 8 @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6@ (" ("k M (! !  @ (E A"!  ("   K"6@  j" O A !  A" 6 Aہ6 A܁6  6  A:t A݁ A݁AĀ"6 E   ƀ A: 6 @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   A !   (j ("j  ( (k"k"k!@ E   j  ( (j! 6 6 6  ("k! )! )! )! )! @ E  (Aj  AjA/:  R  R (! 󂀀! AƁAĀ"6 E   ƀ A: 3 @@ ̀Aj (΀ @@ ̀Aj (΀ ("(!  @ E Aj! ! ( (k! (! (! $ @@ ̀Aj (΀ @@ ̀Aj (΀ ("(!  $ ((! & @@ ̀Aj (΀  @@ ̀Aj (΀  ( Aj! (! & @@ ̀Aj (΀  @@ ̀Aj (΀  ( Aj! (! % @@ ̀Aj (΀  @@ ̀Aj (΀  ( (! # @@ ̀Aj (΀  ( $ @@ ̀Aj (΀  ( ( @@ ̀"AF AG  (΀  ( @@ ̀Aj  (΀  ( & Ȁ  (!A" 6 Aۃ6 A܃6  A: A݃ A݃AĀ"6  ƀ A: & #"E  Aj$  # A # A ǀ A: " A!  A! @@@@@@@@@@  Aq: (! (A6A$" 6 Aǁ6 Aȁ6  A: AɁ AɁAĀ"6 E   ƀ A: ( 6 Aq": Aj!@ -A.G -" E  A.G -E  @ E ) )Q A! ) )Q  (! A"A6 A6 A6  6  6  6  A: A AAĀ"6 E   ƀ A: ' -! Aq:#"E  Aj$A!  -!  ǀ A: # A!  A!  A! ( (k! (! )! )! (! (! (!  р ( 6 6 (!A " 6 Aā6 AŁ6  A: AƁ AƁAĀ"6@  Aj!   ƀ A:  6A0" 6 A6 A6  A:, A AAĀ"6 E  ƀ A:  A! : 6A"B7 Aր6 A׀6 B7  6  6 A6  A: A؀ A؀AĀ"6 E  ƀ A:  6@ A`I A kA瀀 AҀAĀ"6  ƀ A:  @ AJ #Aj! E!  @ ("-A/F #Aj!  @@ -E (E  ( !    ! A݁AĀ"6 E  ƀ A:   ( !   ("A$G  6 (!@ -E  (! 숀 AAĀ"6  ƀ A:  Aj!@ AG A"6  E  ("! 6 6 6  jAjA:AĀ ! AAĀ"6 E  ƀ A:  @ AJ Aj!  )7 )7AÀ ! AAĀ"6 E  ƀ A :  AJ  Aj! ((!  )"7 )"7 (" ("j! )!A!A!  )" R  Q  6 6 7 6 7 Aj6A$"A6 A6 B7 AĀ6  6  A: A AAĀ"6 E  ƀ A :  6 AH A" 6 A6 A6  6  A: A AAĀ"6 E   ƀ A : 6@@   j"F Aj!  A~j"A/: (!@  k"E    @ E (!   O   ! A݁AĀ"6 E  ƀ A: Aj!  ( !  (("6 ("E  󂀀 AƁAĀ"6 E   ƀ A: (("6 Aj! ("E  󂀀 AƁAĀ"6 E   ƀ A: @A (AAAAA"AjAK AA6AA k6 Aj! (! 6 -E ( A<" 6 Aˀ6 À6  A:: A AAĀ"6  ƀ A:  ( (6 Aj! A! -E    (E  (!A<" 6 Aˀ6 À6  A:: A AAĀ"6  ƀ A:  @ ( A"G ( AۙÀA€AA͒ŀς AAĀ"6  ƀ A:  -E  (! 숀 AAĀ"6  ƀ A:  A6 A! 6 Ȁ A6 A WA0" 6 Aރ6 A߃6  6  7  A:( A   ~@@@@@@ -( @@A ( ( (AAA"AjAK AA6AA k"6  A`I A k! 6  A瀀 AҀAĀ"6$  ƀ A:(  @@ ̀Aj ($΀  ( ! ($#Aj 6B!  ! 7 Ȁ A6 A р Ȁ  OA" 6 A6 A6  6  A: A   ~@@@@@ - ) !A"A6 A6 A6  7 A6  A: A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 Ȁ A6 A р Ȁ  ]A0" 6  7 A6 A6  6  6  A:, A   ~@@@@@@@@ -, ( ! )! )!A"A6$ Aր6 A׀6  7  7  6 A6  A: A؀ A؀AĀ"6 E   ƀ A:,  @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  ( "(!  6$ A`I A kA瀀 AҀAĀ"6(  ƀ A:,  A!@@ ̀Aj ((΀  ($! ((#AjA k6 6 Ȁ A6 A р Ȁ  VA " 6 Aҁ6 AӁ6  6  6  A: Aԁ   ~@@@@@ - ) ! (!A8"B7 A6 A6 B7  6  7  A:4 A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 Ȁ A6 Aԁ р Ȁ  VA(" 6 A6 A6  6  6  A:$ A   ~@@@@@@@@ -$ ) ! (!A"A6$ Aր6 A׀6 B7  6  7 A6  A: A؀ A؀AĀ"6 E   ƀ A:$  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 A`I A kA瀀 AҀAĀ"6  ƀ A:$  A!@@ ̀Aj ( ΀  (! ( #AjA k6 6 Ȁ A6 A р Ȁ  OA" 6 A6 A񄀀6  6  A: A򄀀   ~@@@@@ - ) !A"A6 A6 A6  7 A6  A: A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 Ȁ A6 A򄀀 р Ȁ  VA " 6 A6 A6  6  6  A: A   ~@@@@@ - ) ! (!A8"A6 A6 B7 B7  6  7  A:4 A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 Ȁ A6 A р Ȁ  VA(" 6 A6 A6  6  6  A:$ A   ~@@@@@@@@ -$ ) ! (!A"A6$ Aր6 A׀6 B7  6  7 A6  A: A؀ A؀AĀ"6 E   ƀ A:$  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6 A`I A kA瀀 AҀAĀ"6  ƀ A:$  A!@@ ̀Aj ( ΀  (! ( #AjA k6 6 Ȁ A6 A р Ȁ  JA" 6 A6 A6  A: A   ~@@@@@@@@@@@@@@ - @ ( "(8AN A!  ("6 AπkA I ч AAĀ"6  ƀ A: @@ ̀Aj  (΀  ( A还 ((H"E ( !  Aj ! AĀ"6 E   ƀ A:  @@ ̀Aj  (΀  @@ ̀Aj  (΀  ("(!  @ AN A!  @ ( AqAG @ )0"BB B BBQ ( (8E  ( " (Ar6 (H"A AjA?I! 6A0" 6 A6 A6  A:, A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   A!  @@ ̀Aj (΀  (A! 6 Ȁ A6  Ȁ  ( ! (!A "A6 A6 A6   j6  6  6  A: A AAĀ"6  ƀ A: A р FA" 6 A6 A6  A: A  @@@@ - ("B7P  (Ar6A8" 6 A6 A6  A:4 A AAĀ"6  ƀ A:  @@ ̀Aj ( ΀  (! (  A68 Ȁ A6 A р Ȁ  IA" 6 A6 A6  A:` A†   ~@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -`  A! ( "(8"AF  ("AqAG  (lAJ  (! (!A "  k6 AÆ6 AĆ6  6  6  A: Aņ AņAĀ"6 E  ƀ A:`  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  (\"( ! (!A"  kAu6, AƆ6 Adž6  6(  6$  A:T AȆ AȆAĀ"6 E  ƀ A:`  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  A! AH @ Aq A!@ (lAJ ( (I  (\"( (O ("6 AπkA I ч AAĀ"6$  ƀ A:`  @@ ̀Aj ($΀  ($ Ax ( ($"E  ( ! BAA ! AĀ"6( E   ƀ A:`  @@ ̀Aj ((΀  @@ ̀Aj ((΀  ((")!  @ BR AA#Aj(AG!  @ ( "-AqE  (, ($k}! 7 ("6, AπkA I ч AAĀ"60  ƀ A:`  @@ ̀Aj (0΀  (0 Aմ{ (,(@"E  ( ! )!  A ! AĀ"64 E   ƀ A:`  @@ ̀Aj (4΀  @@ ̀Aj (4΀  (4")!  A BS#Aj(AGqk! 68 ( !A" 6 AɆ6 Aʆ6  A: Aˆ AˆAĀ"6<  ƀ A:` @@ ̀Aj (<΀  ( ! (<A! -jA: A;< A;H A]6  Aj6L B7 B7 B7 B7 B7$ B7, A64 B7 A6l B7 B7 B7 B7 B7 B7  Aj6\ AԼπ6 A6` B7p Aغπ6A" 6 A6 A6  A: A AAĀ"6  ƀ A:0 @@ ̀Aj  ( ΀  (! ( ! (! (! ( A" 6( Aↀ6 Aㆀ6  6$  6  6  A: A䆀 A䆀AĀ"6$ E   ƀ A:0  @@ ̀Aj  ($΀  @@ ̀Aj  ($΀  ($"(!  E  ("- (" 7P (\! (! @@ AqE @ ( (O #AjA6B! @ A(! ( "!  (! (!A!  j(! ("(X"6A!@ ("(4 ($"A  ((F! ( (K @ AH B  kAul ( (k|}! (\)47 (! ( !  Aj    kAu! AAĀ"6 E   ƀ A: E @@ ̀Aj3 (΀ / @@ ̀Aj3 (΀ / ("(!  B ("(  ( jk}! (\"6 ("6 ( "6  k!@ AH Au l!   Έ! AAĀ"6 E   ƀ A: B @@ ̀Aj0 (΀ , @@ ̀Aj0 (΀ , ("(!  6 6 ("6 ()47 (! (!  Aj   Aj    kj Aj! AAĀ"6 E   ƀ A: @ @@ ̀Aj. (΀ * @@ ̀Aj. (΀ * ("(!  (!  ) (6 숀 AAĀ"6  ƀ A: > @@ ̀Aj, (΀ ( ( ( (k! ! ("(! -AqE   (k |!  @@ ̀Aj* (΀ & (B! 3  (k |! 7 (")P"BR  ("6 AπkA I ч AAĀ"6  ƀ A: 9 @@ ̀Aj' (΀ # ( Aմ{ ((@"E , (! BA ! AĀ"6 E   ƀ A : 7 @@ ̀Aj% (΀ ! @@ ̀Aj% (΀ ! (")!  B! BQ - ) |"BU ,#AjA6B! , @@ ( (F ( ! (!A!  ( " ("F! :@  K -AqE  A" 6 A눀6 A숀6  A: A툀 A툀AĀ"6@  B! ,  ƀ A : 3 @@ ̀Aj! (΀  @@ ̀Aj! (΀  ("(! @ E B! + ((\! (  ("E  숀 AAĀ"6  ƀ A : 1 @@ ̀Aj (΀  (! (  (A}q6 (!  AAĀ"6  ƀ A : / @@ ̀Aj (΀  (! (  ("6  6  6  6  6  6 (\" ("6  6  6  6  6  6 @@ ("Aj )! , @@ ("(X"("(4 ($" ((F  (\! ( (\! AH ' ( (kAu l ( (k|! ) @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  ' (("6 AπkA I ч AAĀ"6  ƀ A: + @@ ̀Aj (΀  ( A还 ((H"E  (!  Aj ! AĀ"6 E   ƀ A: ) @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  @@  ( AqAF  )!A! ' )@ )|! $ @@ ̀Aj (΀  (! ( (!@ )P"BR (!  (! ( E  Aq  )" Y    ( ("k}"S   6  6  6  6 (\" ("6  6  6  6  6  6    }j6 A쇀! AAĀ"6 E   ƀ A: & @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  E  @@ ̀Aj (΀  (  @@ ̀Aj (΀ @@ ̀Aj (΀ (")!   @@ ̀Aj (΀ (  @@ ̀Aj (΀ @@ ̀Aj (΀ ("(!   @@ ̀Aj (΀ @@ ̀Aj (΀ ("(! A!  @@ ̀Aj  (΀ (! ( ("6 AπkA I ч AAĀ"6  ƀ A:  @@ ̀Aj  (΀  ( Aմ{ ((@"E  (! (! )!    ! AĀ"6 E   ƀ A:  @@ ̀Aj  (΀  @@ ̀Aj  (΀  (")!  B! BQ  (" 7P  ("6  6  6  6  6  6  (Aoq6 (\" ("6  6  6  6  6  6 !  (" (Aoq6 )P"BW  (("6 AπkA I ч AAĀ"6  ƀ A:  @@ ̀Aj (΀  (! ( )P! Aմ{ ((@"E (!  A  AĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ( Ȁ   숀 AAĀ"6  ƀ A:  # A р  Aq ("( 6 (6 ("6 AπkA I ч AAĀ"6  ƀ A:  Aմ{ ((@"E  (! (! )! (!   A  k"k"  } UA ! AĀ"6 E  ƀ A:  7@ BY B!  A! ) ( (k"Aj" U  P  (("6 AπkA I ч AAĀ"6  ƀ A:  ("(! ((8!@@ -E A ) ( (k"Aj"  U!  ( k! A| E  (!    ! AĀ"6 E  ƀ A:  B ) ( (k"Aj"  U" "W B  AF}!A! 6 )! (! (! (" ("6  6  6  6   j6  A   k"Aj"  Uj6 (\" (" 6  6  6  6  6  6 6 (X6 A!  @@@@  (! ("(\" ),74 ( ! (! (\"(! (! A<" Aj60 A6 A6  6,  6(  6$  6  6  A,j6  6  A:8 A AAĀ"6 E   ƀ A: @@@ Aj (" (A r6  (" ) 4|7P (\" (6  (Aoq6  @@#"E Aj$  ǀ A: A!  A! )! 7 Ȁ A6  (! )!   )47, (! (! (\! (! ( !  A,j   kAu! AAĀ"6 E  ƀ A :  (" ( j"6 (\" (6 ( k! ) }!@ ()P"BR A!   |! A! 6 7 (!A" 6 A臀6 A釀6  A: Ă ĂAĀ"6  ƀ A:  6 7 (!A" 6 AɆ6 Aʆ6  A: Aˆ AˆAĀ"6  ƀ A: Aꈀ OA " : A6 A6  6  A: A    A j!@@@@@@@@@@ - ("(X"6@ ("(4 - ($"AH  ((G (\" ( ( ( k mAtj"6   ( 6  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(! A!  # A€ р Ȁ  A! @@@@  (! ("(\" ),74 ( ! (! (\"(! (!A<" Aj60 A6 A6  6,  6(  6$  6  6  A,j6  6  A:8 A AAĀ"6 E   ƀ A:  A!@@@ Aj (" (A r6  ((\"(!  @@#"E Aj$  ǀ A:  A!  A!  6A! 6 Ȁ A6 A WA" 6 A񈀀6 A򈀀6  6  6  A:L A󈀀   @@@@@@@@@@@@@@@@@@@@@@@@@ -L @ (" A!  ( "(! (\"6 ("6@ AqAG ("6 A!  kAu" I  ( Atj!A! (" K  (!A" 6 A􈀀6 A6  6  6  A:L A AAĀ"6( E   ƀ A:L  @@ ̀Aj ((΀  @@ ̀Aj ((΀  (("(!   (k!   kAu! @@ ̀Aj (4΀  @@ ̀Aj (4΀  (4"(!   @@ ̀Aj (<΀  @@ ̀Aj (<΀  (< (8!  # A # A р Ȁ  A!  A!  @@@@@  6$@ A|j"(A G  (kAuAj!A!  #"E  Aj$A!  ($A|j" (K  ( (kAu!  ǀ A:L A! A! :M@  (! (! (!   ("  I"6, (! (!@@ AK  (6 Aj! Aj! AK   ( !@ At"E    (\"  j6  j!  A! @@@@@  6D 6H 6@#"E  Aj$A!  (H! (@" (D"(6 Aj! Aj! A}jA}K  (HAj!  ǀ A:L A! ( 6 (! ( (,k! 60 E  ( !A" 6 A􈀀6 A6  6  6  A:L A AAĀ"64 E  ƀ A:L   (0k! -M  ( (\!  A! -M  68 (" ( "F ( !A"  kAu6, AƆ6 Adž6  6(  6$  A:T AȆ AȆAĀ"6< E  ƀ A:L  ( j! 6 Ȁ A6 A󈀀 [A " 6 A͆6 AΆ6  6  6  6  A: Aφ  @@@@@ - ("(\"("E  -π A )> !~ )!AA6πA >π !~ )!AA6πA >π !~ )!AA6πA >π A )>π A )>π _@ ("AH A AjApq"gk AjAv AK"AK @ A?K A Aj6π A Ar6π @ ("AK A 6π A )>π FA" 6 A6 A6  A: A  @@@@@@@@@@@ - @@ ((" AA6π  A"A6 A6  A:D A AAĀ"6 E   ƀ A:  @@ ̀Aj  ( ΀  @@ ̀Aj  ( ΀  ( "(!  A 6π AK A8"A6 A6  A:3 A AAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  A 6π  @@ ̀Aj (΀  ( Ȁ A6  Ȁ  A "Aπ6 A6 A6 Aπ6 A  AF6  A: A AAĀ"6  ƀ A: A р FA" 6 A6 A6  A: A  @@ -E @ ̀"AF AG р ( ΀E  Ȁ  (6A" Aj6 A6 A6 Aŀ6 A6  A: A AAĀ"6  ƀ A: A (  [A8" 6 A6 A6  6  6  6  A:4 A‰  ~@@@@@@@@@@@@@@ -4 #! ( "(! Aj"6 (6 Aq  (!!  Avj(E (AAHE  (! 所 AڃAĀ"6  ƀ A:4 @@ ̀Aj  ( ΀ (  )! (!A" 6 AÉ6 Aĉ6  7  A:< Aʼn AʼnAĀ"6$  ƀ A:4 @@ ̀Aj  ($΀  (! ($ AAAH  (  @@ ̀Aj  ((΀  ((  @ A K A(π A(πM A A?q"6πA At6π @ (A~q" Axqj"Aj"  k"rAq AjAq" AjqE  A AAĀ"6,  ƀ A:4  @@ ̀"AF AG   (,΀  (, AAπAAx kπA" 6 A6 A6  6  A: ADŽ ADŽAĀ"60 E   ƀ A:4  @@ ̀Aj (0΀  @@ ̀Aj (0΀  (0 ( (6 Ȁ A6  Ȁ  )! (!A" 6 AÉ6 Aĉ6  7  A:< Aʼn AʼnAĀ"6(  ƀ A:4 A‰ р UA" 6 AÉ6 Aĉ6  6  6  A:< Aʼn  @@@@@@@@@@@@@@@@@@@ -<   ( " ("("G Aŀ AAĀ"6  ƀ A:<  @@ ̀"AF AG   (΀  (  ("j! -Aq    (AxqjI AĀ AAĀ"6  ƀ A:<  @@ ̀"AF AG   (΀ ( ("6 Aq AĀ AAĀ"6  ƀ A:< @@ ̀"AF AG   ( ΀ (  @ A I Axq (I  Aŀ AAĀ"6$  ƀ A:< @@ ̀"AF AG  ($΀  ($ @A("E Axj"E Aj   @ ( "-AqE (!  ("6(  k"(!  AxqF A AAĀ"6,  ƀ A:<  @@ ̀"AF AG  (,΀  (, @@ ̀Aj  (0΀  (0 ( (("k! ( j! (! (! ( ! (!A0" Axq6 AƉ6 Alj6   j6  6  6  6  A:, Aȉ AȉAĀ"64 E   ƀ A:<  @@ ̀Aj (4΀  @@ ̀Aj (4΀  (4"(!  (!A" 6 Aɉ6 Aʉ6  6  A:l Aˉ AˉAĀ"68  ƀ A:<  @@ ̀Aj (8΀  (8 Ȁ A6  Ȁ  A" 6 Ả6 A͉6  A: AΉ AΉAĀ"60  ƀ A:< Aʼn р FA" 6 Ả6 A͉6  A: AΉ  @@@@@@@@@@@@@ - ("("Axq"  j(F A"A6 A6 A6  A: A AAĀ"6  ƀ A: @@ ̀"AF AG   ( ΀ (  @ ("( G ( "( F  A͍ AAĀ"6  ƀ A:  @@ ̀"AF AG   (΀ (  6  6 AI  ("("E @ ( G ("( F  A"Aŀ6 A6 A6  A: A AAĀ"6  ƀ A:  ̀"AF  AG  р (΀  ( @ ( @  G  6  6   6  6 ( 6 ( 6   6 ( 6 Ȁ A6 AΉ Ȁ  dA0" 6 AƉ6 Alj6  6  6  6  6  A:, Aȉ   @@@@@@@@@@@@@@@@@ -, (! (" ( "(F  j-Aq A" 6 Ả6 A͉6  A: AΉ AΉAĀ"6  ƀ A:,  @@ ̀Aj ( ΀  (! (! (   j!   (A~q6 (! ( ! AI  ("( AjF A AAĀ"6$  ƀ A:, @@ ̀"AF AG   ($΀ ($ (B7 ( Aj!   Av"Atj"("( Aj"F A AAĀ"6(  ƀ A:,  ̀"AF  AG  р ((΀  ((  Aj"AvAqj" (A tr6 (" 6  6  Ar6  6  6  j 6  (!  ("6   j"Ar6 6 Ȁ A6 Aȉ Ȁ  NA" 6 Aɉ6 Aʉ6  6  A:l Aˉ   @@@@@@@@@@@@@@@@@@@@ -l  ( AI @ ("AπG A(π"(Axq"A(πI  Aoj"A(π"M A!  kAA(π"A kq"E @A- @A(Ğ @A AAAAAA"AjAK AA 6AA k6 A 6Ğ AA(Ğ" AF!A(π!   jG A- A kA- @A(Ğ @A AAAAAA"AjAK AA 6AA k6 A 6Ğ AA(Ğ" AF"E   F AA(π  k"k6πA(π  kAr6  (A@q"("6  F A<"Aŀ6$ A6 A6 A#6 A€6 A6  A:; A AAĀ"6  ƀ A:l  @@ ̀"AF AG   (΀ ( A(π6 (" AjG (" ("Axj"  jAq"k"j" (AG Aj! A! @@ ̀"AF AG   (΀  ( @@ ̀"AF AG   (0΀  (0 @@ ̀"AF AG   (4΀  (4 @@ ̀Aj (<΀  @@ ̀Aj (<΀  (<A!  @@ ̀Aj  (D΀  (D ( (, (@jk!A!  @@ ̀"AF AG  (L΀  (L @@ ̀"AF AG  (P΀  (P @@ ̀Aj  (h΀  @@ ̀Aj  (h΀  (h"(!   Ȁ  @# A A! @@@@@@@@@  6$ 6( 6 ("6,@    kj" (" Axqj"AjAI AŀA܂€AAŀς AAĀ"60  ƀ A:l Aj!@ Aq ( j"AjA?I AA܂€AAŀς AAĀ"64  ƀ A:l 68  kAj ( (jAjI (" ( (k6@ AjA(G AA6 A"A6 A6 A6  6  A: ADŽ ADŽAĀ"6< E   ƀ A:l ((" ( (,k"j" -Aq  ("6@A"   kj6 Ả6 A͉6  A: AΉ AΉAĀ"6D  ƀ A:l 6H@ (("(Aj  j" (8"jqE A<"Aŀ6$ A6 A6 A6 A܂€6 AÀ6  A:; A AAĀ"6L  ƀ A:l @  j ($(F A<"Aŀ6$ A6 A6 A6 A܂€6 Aŀ6  A:; A AAĀ"6P  ƀ A:l (!  Ar6 6@ AF ((!  #"E  Aj$A!  (("(" ("Axj"  jAq"k"j" (AG  Aj!  (Hj!  ǀ A :l  A!  A!  A! A<"Aŀ6$ A6 A6 A6 A܂€6 Aŀ6  A:; A AAĀ"6  ƀ A:l  6T 6X ("6\ Axq"A(πI  Aoj"AH   ("M  ("6`  kA kq"E  ("6d  k"AH @A- AA:   j AA2AB! AƄAĀ"6h E  ƀ A :l  AF (T! (! (X" (d (\Axq" (kAojA (`kq"k"6  6  ( k6   kAr6 Ȁ A6 Aˉ р HA0" 6 A6 A6  A:, A   @@@@@@@@@@@@@@@@@@@ -, ( "AjApqA AJ"A(πO  Apj"AK #Aj(" Av"Atj"("E  AqE A AAĀ"6  ƀ A:,  @@ ̀"AF AG  (΀  ( A6 Aj A v (s6  Atj" /Aj;  g"6 #Aj("6 A kAtj"("E A|j(Axq" O  A v" ("F  s"A|j(Axq" O A v" ("F !A!  @@ ̀"AF AG   ($΀  ($  F  @@ ̀Aj ((΀  @@ ̀Aj ((΀  (("(!  # A Ȁ  A! @@@@@  6 6 @ ( "AH AjApq  sA|j(Axq"M  #"E  Aj$A!  ( ( s"A v" ("G   ǀ A:, A! р Aq  Aj! A v (s!  ( "AH  AjApq G  A v s"Aq  sA v (s! ! !  A AAĀ"6$  ƀ A:,  (! (!  6 A6 A kAtj" /Aj;  ( ! ш! AωAĀ"6( E  ƀ A:,  6 Ȁ A6 A IA" 6 AЉ6 Aщ6  A:@ Aω   @@@@@@@@@@@@@@@@@@@@@@@@@@@ -@   Avj(  ( !Aπ Ԉ! A҉AĀ"6 E   ƀ A:@  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  E  A|j(AqAG  AxjA@q(AπF AŀA€AAŀς AAĀ"6  ƀ A:@  @@ ̀"AF AG   (΀  ( #Aj("6 E  AAHE  所 AڃAĀ"6  ƀ A:@  @@ ̀Aj Aj! (!  (΀  Aj! (!  ( !A"A6 AӉ6 Aԉ6  6  A:` AՉ AՉAĀ"6 E   ƀ A:@  @@ ̀Aj  ( ΀  @@ ̀Aj  ( ΀  ( "Aj! (!  6$ ( !A" 6 A։6 A׉6  6  A: A҉ A҉AĀ"6(  ($!  @@ ̀Aj  ((΀ @@ ̀Aj  ((΀ (("(!  ($!   E @ AAAH ($ Aπ! ($AπF AAAHπE Aπ所 AڃAĀ"6,  ƀ A:@  @@ ̀Aj  (,΀ (,!Aπ!  ( ! Aπ׈! AՉAĀ"60 E   ƀ A:@ @@ ̀Aj (0΀  @@ ̀Aj (0΀  (0"(!  64 ( !A" 6 A։6 A׉6  6  A: A҉ A҉AĀ"68 E   ƀ A:@ @@ ̀Aj (8΀  @@ ̀Aj (8΀  (8"(!  (4! @ E AAAH  E  A|j("Aq Aπ!@ AqE AxjA@q(!  F AŀA€AAŀς AAĀ"6<  ƀ A :@  ̀"AF  AG  р (<΀E  Ȁ   ƀ A:@  (< A! 6 Ȁ A6 Aω QA" 6 A։6 A׉6  6  A: A҉   ?@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -! "#+%&'()* @ ("AJ #AjA 6A! = Aj"Apq! ( "  A! A؉AĀ"6 E   ƀ A: = @@ ̀Aj4 (΀ # @@ ̀Aj4 (΀ # ("(!   A! ; A("E : ("E :  As  : AK   Av"Atj"("6@  Aj"G Aj!  ( "( F A AAĀ"6  ƀ A: : @@ ̀"AF AG  1 (΀ (  6  6  j" (Ar6@ AπF  (Ar6 (AjAvA(πO 6 #Aj"6 ("ÀG  ( ! ㈀ AىAĀ"6$  ƀ A: 8 @@ ̀Aj/ ($΀  ( ! ($ (! 6(  ("AjAvAqj/"E 4 ( AjAvAqj"(" AjF 4A! + @ AK AvA1j!  @ AK A vAj!  @ AK A vAj!  @ A K AvAj!  AvAjA A/I! 6, A(π60 (" AjF + #Aj64 ("Axq"A I 1 Aj!  j! A! A! A! A! ( @@ ̀"AF AG  + (L΀  (L @@ ̀"AF AG  * (P΀  (P @@ ̀"AF AG  ) (T΀  (T @@ ̀"AF AG  ( (X΀  (X @@ ̀"AF AG  ' (\΀  (\ @@ ̀Aj& (`΀  (`A! " @@ ̀"AF AG  % (h΀  (h @@ ̀"AF AG  $ (l΀  (l @@ ̀"AF AG  # (p΀  (p @@ ̀"AF AG  " (|΀  (| @@ ̀"AF AG  ! (΀  ( @@ ̀"AF AG  (΀  ( @@ ̀"AF AG   (΀  ( @@ ̀"AF AG   (΀ ( @@ ̀Aj (΀ (! (! ( ( ! (!@  AjApqkAK  (j" (Ar6 AπF  (" (Ar6  ("( Aj"F A AAĀ"6  ƀ A: % @@ ̀"AF AG   (΀ ( (!  (AjApq"j" 6  6  6  6 @  kAI B7 (! ("AA ( AπF (AjApq"r6  j  k"6  Ar6 (Aj!A("E ! ("E !  As  ! @@ ̀"AF AG   (΀  ( @@ ̀"AF AG   (΀  ( @@ ̀Aj (΀  (! (! ( ( !@  AjApqkAK ( (Axqj" (Ar6 AπF  (" (Ar6  ("( Aj"F AÀ AAĀ"6  ƀ A:  @@ ̀"AF AG   (΀  ( ( ("AjApqj" 6  6  6  6 @ AK ( 6 @ ( (AjApqkAI B7 (! ("AA ( AπF (AjApq"r6  Axq"j  k"6  Ar6 (Aj!A("E  ("E   As   @@ ̀"AF AG   (΀  ( @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   A!  Ȁ  # A # A # A # A # A # A @# A A!  A!  A!  A!  A!  A!  A!  @@@@@@@@@@@@@@@@@@  6D 6H 6@ 6< 68  ( "("K @@ ("AI  M  Aŀ AAĀ"6P  ƀ A:  @ (Axq F Aۧŀ AAĀ"6T  ƀ A:  @@ ( "( G ( Aj"F  A AAĀ"6X  ƀ A:  @ AqE Aըŀ AAĀ"6\  ƀ A:  ("Aj!@ AK  G  ( G  Aq"AjM   j"6  6  6  6  6@  k"AI B7 Aj! AA ( AπF (AjApqr6 6  Ar6A("E  ("E   As    6  6  ApqG  ( ! Ar6@ AπF (Ar6 (4(ÀG  ( ! ㈀ AىAĀ"6`  ƀ A :  @ ("AjAv" (0O A! (4(" Atj"/"E (H" Aj"A v  Atj"(s6 A(6  Aj;  6 (  ;<  ;:  ;8  ;6  ;4  ;2  ;0  ;.  ;,  ;*  ;(  ;&  ;$  ;"  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; Ȁ A6 Aى р Ȁ  VA4" 6 Aꉀ6 A뉀6  6  6  A:0 A쉀   @@@@@@@@@@@@@@@@@@ -0 ( ! (! (!A8"A6$ B7 Aቀ6 A≀6  A"r6 A6 A6   jAjA kq6  A:4 AƄ AƄAĀ"6 E   ƀ A:0  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6A! AF ( A(πAG  (" ( jAjA kq"A(πI @@ Aq !   AjA`q"k j!   A A䉀AĀ"6 E   ƀ A:0  @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  (  ( ! (! (!A "A6 A6 A6  6   jAjA kq6  A: A㉀ A㉀AĀ"6$  ƀ A:0 @@ ̀Aj ($΀  ( ! (! (! (! ($ Aj AGAr6 A j  jAjA kqArApj6 AAπ"6(A(π" J A!  # A # A р Ȁ  A!  A!  @@@@@  A  ((AjHπ F #"E  Aj$A!  A(π" ((L   ǀ A:0  A! A (" ( jAjA kq"π"6,A(π"  jO A! @@@@@  A  (" ( jAjA kq (,jHπ F #"E  Aj$A!  A(π" (" ( jAjA kq (,jI   ǀ A:0  A! (Aj! 6 Ȁ A6 A쉀 MA" 6 A򉀀6 A󉀀6  6  A: A퉀  @@@@@ - A(πAG  ( "A(πI @ ("AqE  j AjA`q"k! A "A6 A􉀀6 A6  6  6  A: A䉀 A䉀AĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ( Ȁ A6 A퉀 р Ȁ  FA<" 6 Aˀ6 À6  A:: A  @@@@@@@@@@@@@@@@@@@ -: ("E  A|j("6 AqE A AAĀ"6  ƀ A::  @@ ̀Aj  (΀ (  Axq"A(πO  (! A("6  G  򈀀 AAĀ"6  ƀ A::  @@ ̀Aj  (΀ ( @@ Apj"AK #Aj(" Av"Atj"/"E   A v  Atj"(s6  6  Aj;  6  g"6 #Aj("6 AI A k"Atj/";8 E  Atj"Aj!@ ("  6 (!A! ! @ A|j(Axq I  6 (! ! ! A v" ("F  s"A|j(Axq O ! A v" ("F A! ÀG   AAĀ"6,  ƀ A:: @@ ̀Aj (,΀  (, A k Axj"O A AAĀ"60  ƀ A:: @@ ̀Aj (0΀  (0 Aπ!@ AqE A@q(!    A A‰AĀ"64  ƀ A:: @@ ̀Aj (4΀  (4  # A р Ȁ  A! @@@@@  6$ 6(  sA|j(Axq ( AxqO #"E  Aj$A!  ($ ((s"A v" ("G   ǀ A::  A! (" (6  A vs!  s! ( ! (! /8! ( A v s6  6 A kAtj Aj; Ȁ A6 A FA" 6 A6 A6  A: A  @@@@ - A(E  Ȁ A6  @ ̀"AF AG р ( ΀E  Ȁ  (!A" 6 A6 A6  A: A AAĀ"6  ƀ A: A (  FA8" 6 A6 A6  A:4 A  @@@@@@@@@@@@@@@ -4  @@ ̀Aj (΀ ( Ȁ A6 #Aj(6 A! A(π6A! @@ ̀"AF AG   (΀  ( @@ ̀"AF AG   ((΀  (( ̀"AF  AG  р (,΀  (, # A # A Ȁ  A!  A! @@@@@@@@@@@  6 ( Atj("E A! (  (Aj!  ($Aj" (F  ( A v (0s! 6 6$@ AqE AÀ AAĀ"6(  ƀ A:4  @  (G A"AÀ6 A6 A6  A: A AAĀ"6,  ƀ A:4  ("60  A vG  @ (AG ("A6 숀 AAĀ"6  ƀ A:4  #"E  Aj$A!  #"E  Aj$A!  ǀ A:4  ǀ A:4  A! A"A6 A6 A6  A: A AAĀ"6  ƀ A:4 A FA" 6 A6 A6  A: A  @@@@@@@@@ - #Aj"6 À6A(πE Aш! AωAĀ"6    6  @@ ̀Aj (΀  @@ ̀Aj (΀  ( ! ("(!   6   ( À6  @@ ̀Aj (΀  ( Ȁ A6  Ȁ   ƀ A:  р AjAA A/π";  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;~  ;|  ;z  ;x  ;v  ;t  ;r  ;p  ;n  ;l  ;j  ;h  ;f  ;d  ;b  ;`  ;^  ;\  ;Z  ;X  ;V  ;T  ;R  ;P  ;N  ;L  ;J  ;H  ;F  ;D  ;B  ;@  ;>  ;<  ;:  ;8  ;6  ;4  ;2  ;0  ;.  ;,  ;*  ;(  ;&  ;$  ;"  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; (!A<" 6 Aˀ6 À6  A:: A AAĀ"6  ƀ A: A PA" 6 Aہ6 A܁6  6  A:t A݁   @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -t  (! ( " A0" 6 A6 A6  A:, A AAĀ"6 E $  ƀ A:t % @@ ̀Aj# (΀  @@ ̀Aj# (΀  ("(!  #  A<" 6 Aˀ6 À6  A:: A AAĀ"6  ƀ A:t # @@ ̀Aj! (΀  (A! ! A|j("6 Axq!@@ Aq"E A|j!  A A|j" j(Aqk q! 6 @  I  kAI ! @ Aq Axj"A kM  A AAĀ"6$  ƀ A:t ! @@ ̀"AF AG   ($΀  ($ @ AJ #AjA 6A!  AjApq! E ("6( A(π"6,@ A Aq"Aj"  A~q"jAj"  k"rq  q" AjqE  A AAĀ"60  ƀ A:t  @@ ̀"AF AG   (0΀  (0   j jAjA kq"F    AAߎ! AAĀ"64 E   ƀ A:t  @@ ̀Aj (4΀  @@ ̀Aj (4΀  (4"(!  68 AF  (("A~q" (AxqjAjA(π"O A(πAG   (,A Aq"j (AjApqjAjA kq" I @@ Aq !   AjA`q"k j!   A A䉀AĀ"6< E   ƀ A:t  @@ ̀Aj (<΀  @@ ̀Aj (<΀  (< (! (! (,! (("A~q" (8j" 6   A Aq"j AjApqjAjA kq" kArAxj6 A  Axq jk"π"6@A(π"  jO A!  @ (" ( K ( !   Έ! AAĀ"6D E   ƀ A:t  @@ ̀Aj (D΀  @@ ̀Aj (D΀  (D"(!   A!  6H ( !@ (AxqAxj"E     Axj AAĀ"6L  ƀ A:t  @@ ̀Aj (L΀  (L (H!  Aπ!@ AqE A@q(! 6PAvj(     ! AAĀ"6T E   ƀ A :t  @@ ̀Aj (T΀  @@ ̀Aj (T΀  (T"(!   A!  A|j("Aq Aπ!@ AqE AxjA@q(! (P F AŀA€AAړŀς AAĀ"6X  ƀ A :t  @@ ̀"AF AG   (X΀ (X AAHE  所 AڃAĀ"6\  ƀ A :t  @@ ̀Aj (\΀ (\ (! ( ! (! (P!  Axj Axq AjApq! AAĀ"6` E   ƀ A :t  @@ ̀Aj  (`΀  @@ ̀Aj  (`΀  (`"(!  @ (PAAAH (P E  A|j("Aq Aπ!@ AqE AxjA@q(! (P F AŀA€AAړŀς AAĀ"6d  ƀ A :t @@ ̀"AF AG  (d΀  (d (! Έ! AAĀ"6h E   ƀ A:t @@ ̀Aj (h΀  @@ ̀Aj (h΀  (h"(!   A!  6l (P!@ ( "A|j"(AxqA|j"E    (!  Axj AxqA A‰AĀ"6p  ƀ A:t  @@ ̀Aj (p΀  (p (l!  # A Ȁ  A! @@@@@  @A  (@ (("A~q" (Axqjk  (,A Aq"j (AjApqjAjA kqjHπ G ((A~q (8j!  #"E  Aj$A!  A(π" (@ (("A~q" (Axqjk  (,A Aq"j (AjApqjAjA kqjI   (8j!  ǀ A:t  A! р Aj! 6 Ȁ A6 A݁ FA" 6 A6 A6  A: A  @@@@@@@@@@ - ("("Aq A<"Aŀ6$ A6 A6 A6 A€6 Aŀ6  A:; A AAĀ"6  ƀ A:  @@ ̀"AF AG  ( ΀  (  @ (A~q" Axqj"Aj"  k"rAq AjAq" AjqE  A AAĀ"6  ƀ A:  @@ ̀"AF AG   (΀  ( AAπAAx kπA" 6 A6 A6  6  A: ADŽ ADŽAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ( Ȁ A6 A Ȁ  р ^A" 6 A6 A6  6  6  6  A:D A   @@@@@@@@@@@@@@@@@@@@@ -D  @ ("("A I (" AxqG  ( "("I  A AAĀ"6  ƀ A:D  @@ ̀"AF AG   (΀ ( AqE A<"Aŀ6$ A6 A6 A#6 A€6 Aŀ6  A:; A AAĀ"6  ƀ A:D  @@ ̀"AF AG  ( ΀ (   j"("6$@ A I Axq" I  A AAĀ"6(  ƀ A:D  @@ ̀"AF AG  ((΀ ((  ("O @  (G  j" AjI  AA AπF Aqr r6   j"6   kAr6 Aj!  j I   j(Aq  ň AΉAĀ"6,  ƀ A:D @@ ̀Aj  (,΀  (, ($Axq (j!  A" Aqj6 A։6 A׉6  6  A: A҉ A҉AĀ"60 E   ƀ A:D @@ ̀Aj (0΀  @@ ̀Aj (0΀  (0"(!   A!  64@ Axj (" ("jG A|j(Axq j!  ( !@ (AxqA|j"E  Aj  (!   AxqA A‰AĀ"68  ƀ A:D @@ ̀Aj (8΀  (8 (4!  @@ ̀"AF AG   (<΀  (< @@ ̀Aj (@΀  (@  Ȁ  р @  ("O A<"Aŀ6$ A6 A6 A$6 A€6 Aŀ6  A:; A AAĀ"6<  ƀ A:D  ( ! (!  k"AK   (AqAA AπFr r6  j" (Ar6 (Aj! 6 Ȁ A6   (Aq rAA AπF"r6  j"  rAr6  j" (Ar6 (!A8"A6 A6 A6  Axq6  6  6  A:4 A‰ A‰AĀ"6@  ƀ A:D A OA8" 6 A6 A6  6  A:4 A   ~@@@@@@@@@@@@@@@@@@@ -4 5 5~""6@ B E #AjA 6A!  AjApqA AJ"A(πO  Apj"AK #Aj(" Av"Atj"("E  AqE A AAĀ"6  ƀ A:4  @@ ̀"AF AG  (΀  ( A6 Aj A v (s6  Atj" /Aj;@ AqA r"A(I E  A   A6 A6  j"AxjB7 AI  B7 ApjB7  g"6 #Aj("6 A kAtj"("E A|j(Axq" O  A v" ("F  s"A|j(Axq" O A v" ("F !A!  @@ ̀"AF AG   (,΀  (,  F  @@ ̀Aj (0΀  @@ ̀Aj (0΀  (0"(!  # A Ȁ  A! @@@@@  6$ 6(@ ("AH AjApq  sA|j(Axq"M  #"E  Aj$A!  ($ ((s"A v" ("G   ǀ A:4 A! р Aq  Aj! A v (s!  ("AH  AjApq G  A v s"Aq  sA v (s! ! !  A AAĀ"6,  ƀ A:4  ( ! (!  6 A6 A kAtj" /Aj; A|j(AxqA|j"E  A   (! ! AAĀ"60 E  ƀ A:4  6 Ȁ A6 A IA" 6 A6 A6  A:@ A   @@@@@@@@@@@@@@@@@@@@@@@ -@ @Avj( A(π"(Axq!Aπ!A!  #Aj("6 E  AAHE  所 AڃAĀ"6  ƀ A:@  @@ ̀Aj  (΀ ( (! ( !A"A6 AӉ6 Aԉ6  6  A:` AՉ AՉAĀ"6   ("(Axq! @@ ̀Aj  (΀  @@ ̀Aj  (΀  ("(!   A!A!A!A! @@ ̀Aj  ((΀  @@ ̀Aj  ((΀  (("(!   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($Aj"j-"A G   ǀ A:3  A! 6 Ȁ A6 A BA"A6 A6  A:D A   Aj!@@@@@@@@@@@@@@@@@@ -D A("A؃6 Aك6 B7 A6  A:$ A AAĀ"6 E   ƀ A:D  @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  ( "(!  6( AF A("A6 A6 A6  6  6  A:$ A AAĀ"6, E   ƀ A:D @@ ̀Aj (,΀  @@ ̀Aj (,΀  (,"(!  60 AK  ((!  jA:A" 6 AɃ6 Aʃ6  A: A˃ A˃AĀ"64 E   ƀ A:D @@ ̀Aj  (4΀ @@ ̀Aj  (4΀ (4 (0AG  ÀA! AAĀ"68 E   ƀ A:D  @@ ̀Aj  (8΀ @@ ̀Aj  (8΀ (8"(!  @  A!   ÀA! AAĀ"6< E   ƀ A:D  @@ ̀Aj (<΀  @@ ̀Aj (<΀  (<"(!  @  A!   ÀA! AAĀ"6@ E   ƀ A:D  @@ ̀Aj (@΀  @@ ̀Aj (@΀  (@"(!   A!  A! 6 Ȁ A6 A р Ȁ  YA " 6 A6 A6  6  6  A: A  ~ Aj! Aj!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -   ( ! ( ! ( A6 A6  A("A؃6 Aك6 B7 A6  A:$ A AAĀ"6 E   ƀ A: , @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  ( "(!  6 B! AG ! ( A6 ) @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  ( "(!  ! @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  ( "(!   !A "A 6 A6 A6  6  A: A AAĀ"6 E  ƀ A: ( @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  ( "(!   $ @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  (  $ @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  (  ! A6 A(" A j6 A؃6 Aك6 A6 A6  A:$ A AAĀ"6 E   ƀ A: $ @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  ( "(!  6 AF !A("A6 A҃6 AӃ6  6  6  A:$ Aԃ AԃAĀ"6 E   ƀ A: " @@ ̀Aj  ( ΀ @@ ̀Aj  ( ΀ ( "(!  AjA~O A!  @@ ̀Aj  ( ΀ @@ ̀Aj  ( ΀ ( "(! A!  @@ ̀Aj  ( ΀ @@ ̀Aj  ( ΀ ( "(!    ( "-APjAq"A K A! -" APjAqA I  @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  (   6 #"E  Aj$  # A # A # A # A # A р Ȁ  ǀ A :  A!  A!  A! A!  A! @@@@@  : 6 6 #"E  Aj$A!  ( A l - APjAqj! ( ( Aj"j-" APjAqA O   ǀ A :  A! ) ( kAj|!  A t ( "G ( ! ( 6  hAtAr6  A! @@@@@@@@@@@@  6 !  6 AjA~O #"E  Aj$A! ( !  @ ( / j  ( jG ( !A("A6 A҃6 AӃ6  6  6  A:$ Aԃ AԃAĀ"6 E   ƀ A :  #"E  Aj$A!  ( / j! 6 /; -A.F A"A 6 A6 A6 AĀ6  Aj6  A:< A AAĀ"6 E   ƀ A :  ǀ A:  ǀ A:  A!  A!  A! ( !A" 6 AɃ6 Aʃ6  A: A˃ A˃AĀ"6 E   ƀ A : 7 ( !A0"A6  7 A6 A6  6  6  A:, A AAĀ"6 E  ƀ A:  AH   jA:A"A€6 AՂ6 Aւ6  6  A: A AAĀ"6 E  ƀ A:  6 -"APj!@ A F" AqA K  A  ! A! @ -"A F APjAqA O  A! @@@@@  : 6 6 #"E  Aj$A!  ( " A l - "jAPj A F! ( ( Aj" j-"A F  APjAqA O   ǀ A:  A! 6 ( !A" 6 AɃ6 Aʃ6  A: A˃ A˃AĀ"6 E  ƀ A:  ( ( A t"6 E  ( ( A thAtAr6  ( !A" 6 AɃ6 Aʃ6  A: A˃ A˃AĀ"6 E  ƀ A:  ( A6 Ȁ A6 A ?A"A6 A6  A: A  @@@@@@@@@@@ - A "A6 A6 A񃀀6 A6 À6  A: A򃀀 A򃀀AĀ"6 E A!  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  6A " Aj6 A6 A6 Aŀ6 A6  A: A AAĀ"6 E A!  @@ ̀Aj ( ΀  @@ ̀"AF AG   ( ΀  (  A AAĀ"6A!  ƀ : A ̀"AF  AG  р (΀E  Ȁ  ( NA" 6 A6 A6  6  A:H A  @@@@@@@@@@@@@@@@@@@@@@@@@ -H ("(6 ( "6 ("6 ( (j  k"j AujAj" ("  J"6 (! -(AqE  ($!A还 E    ! AĀ"6 E   ƀ A:H  @@ ̀Aj  ( ΀ @@ ̀Aj  A j!  ( ΀ A j!  A鼳 E   ! AĀ"6$ E   ƀ A:H  @@ ̀Aj  ($΀ @@ ̀Aj  A$j!  ($΀ A$j! ("(!  6(  AAE A"A6 A6  A: A AAĀ"6, E   ƀ A:H  @@ ̀Aj (,΀  (, (! (! ((" (6  6   j"6  6 ("60A! AH ( (k"Av"E (("64@ Aq"E AvAq!  AtA|j"j!  jAj Asq j!@  (6 A|j! A|j! Aj" ! ( (kAI A! @@ ̀Aj Aj!  (@΀  Aj!  @@ ̀Aj Aj!  (D΀  Aj! ( # A # A р Ȁ  A!  A!  @@@@@  68 (( (0"jAj Asq" At"A|j"j (4" j(6  Axj"j  j(6  A}j"At"j  j(6  Apj"j  j(6 AM #"E  Aj$A!  (8A|j!  ǀ A:H  A! ( (kA|q!  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Awj("6A!@  AqApj41111111111111111111111111111111111111 (!Awj Aj6A! , @@ ̀"AF AG   ( ΀  (   "6$@ Aq"E (!Awj AjAr6 @ ("(Aq G @@ AqAj AwjA6A#! 0 A!AwjA6@ (Aj" A ! 0  6 / A HE A!@   Aq! 6( (!A$" 6 A6 A6 B7  6  A: A AAĀ"6, E   ƀ A:l / @@ ̀Aj (,΀  @@ ̀Aj (,΀  (,"(!  ($! AF  A#G  AqA}jA~I AŀAƀ€AAŀς AAĀ"60  ƀ A:l - @@ ̀"AF AG   (0΀  (0 AqE AAƀ€AAŀς AAĀ"64  ƀ A:l + @@ ̀"AF AG   (4΀  (4 @@ ̀Aj (8΀  @@ ̀Aj (8΀  (8A!  ("(Aq! Aq  E AÀAƀ€AAŀς AAĀ"6<  ƀ A:l ( @@ ̀"AF AG   (<΀  (< E A{, B7 Awj(6Awj AjAr6AwjA6A! % (! -$AqE  (AG  A6@@A AAAAA"AjAK AA6AA k6  A`I  @@ A&j& AF  Aƀ A񀀀AĀ"6@  ƀ A:l % @@ ̀"AF AG  (@΀  (@ AwjA6A! " A6 Awj(6Awj AjAr6AwjA6  A6  (!  ! (6D@ ( G A#!@ AqAj! @ (Aj" A ! !  6  A "AΊ6 Aϊ6  A: AЊ AЊAĀ"6H E   ƀ A:l @@ ̀Aj (H΀ @@ ̀Aj (H΀ (H"(!  A!  (D"Av"L A!  @@ ̀Aj (P΀  @@ ̀Aj (P΀  (P"(!   @@ ̀Aj (T΀  @@ ̀Aj (T΀  (TA!  @@ ̀Aj (`΀  @@ ̀Aj (`΀  (`"(!    ( (\A`q" Ar"H F  (  ArH"A`q G A!  @@ ̀"AF AG   (d΀  (d ̀"AF  AG  р (h΀  (h Ȁ  Ax!# A # A # A # A # A A! A!  A! @@@@@  @  (\A`q"F @@A ("  AsAq ArAAA"AjAK AA6AA k6  A`I  @ A j Aƀ A񀀀AĀ"6d  ƀ A :l  ( (\A`q" ArH F #"E  Aj$A!  ( (\A`q"Ar ArH"A`q G   ǀ A:l  A! @@@@  A6 ((!A(" 6 A6 A6 A6 B7  6  A:$ A AAĀ"68 E   ƀ A:l  @@#"E Aj$  ǀ A:l  A!  A! @ ("(E A<"Aŀ6$ A6 A6 A6 Aƀ€6 AÀ6  A:; A AAĀ"6h  ƀ A :l A6  6LA "AΊ6 Aϊ6  A: AЊ AЊAĀ"6P E  ƀ A :l @  (LAvL (X!A"A6 Aъ6 AҊ6  6  A:d Aӊ AӊAĀ"6T@  A!  ƀ A :l #"E  Aj$ (L"Av! (X!  ǀ A:l  6X 6\A" 6 Aъ6 AҊ6  6  A:d Aӊ AӊAĀ"6` E   ƀ A :l  A! @@@@  6 (!  Aj! @@@@@@ (" (A ( (rH"E  @@@@ AqE (  ( Axqr (rH" G  ("B7 Awj(6Awj Aj6AwjA6A! @ Aq (G @@ (" AqAoj AwjA6A#! A!AwjA6@ (Aj" A !  6 @@ AN !  (  Axr"H" G  A (A AAA"AjAK AA6AA k6  6#"E  Aj$A!  A`I  A j @ ("(AG A6@ AAAH (A쉀 AwjA6A!  A6 Awj(6Awj Aj6AwjA6  Aƀ A񀀀AĀ"6  ƀ A:l  @#"E Aj$Ax!  ǀ A:l  ǀ A:l  A! (" (6  (Aj6 A! 6 Ȁ A6 Aʊ FA" 6 AԊ6 AՊ6  A: Aˊ  @@@@@ - @ ( Aq" Avj( ("( A6  (AAHE  (!  鉀 AAĀ"6  ƀ A:  @@ ̀Aj ( ΀  (  Ȁ A6 Aˊ р Ȁ  OA" 6 A֊6 A׊6  6  A: A؊   @@@@@@@ - ( " Aq"AI  (!  ! AيAĀ"6 E   ƀ A:  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   E @@ Aj @ (Awj(F A!  ( " (Aj"6 E A!  A! (Awj(G  ( (   р Ȁ  (! ( A6@ E ( " (Aj6 @  Aq" Avj( A! ( A6  A! ( AAAH ( 쉀 6 Ȁ A6 A؊ PA" 6 Aڊ6 Aۊ6  6  A:@ Aي   @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@   A!@@@@ ( " AqApj4************************************ * (!! (!@ Aq Awj(G AG ( " (Aj"6 E A! * @ Awj(F A! * ( " (Aj"6A! E  ) A! (AqAwj(G ( ( "(E (A! (AG  A! 6 ( !Awj Aj"6Awj(A~q"(!  F   A~q"G  $ @@ ̀"AF AG   (΀ ( @ (Awj(F A! % ( " (Aj"6A! E  $ (!! (!@ Aq Awj(G AG ( " (Aj"6 E A! $ @ Awj(F A! $ ( " (Aj"6A! E  # A! (AqAwj(G " ( "(E "A!  AqE  (AG  A!  AqE  6 ( !Awj Aj"Ar6Awj(A~q"(!  F  A~q"G   @@ ̀"AF AG   ($΀  ($ @ (Awj(F A!  ( " (Aj"6 E A!  A! (Awj(G  ( (AqE  (! ( A6@ E ( " (Aj6 ( ""   A`qH"F A!  @@ ̀"AF AG   (,΀  (, @@ ̀Aj (0΀  @@ ̀Aj (0΀  (0"(!   Ȁ  # A # A # A # A Awj 6  Awj 6 A! A!  A!  A!  A!  A! @@@@@  68#"E  Aj$A!  ( Aj (8"(A~q"F   ǀ A:@  A! @@@@@  64#"E  Aj$A!  ( Aj (4"(A~q"F  ǀ A:@  A! @@@@@  6<#"E  Aj$A!  (<" (  A`qH"G  (A! (6, A\j-:] ( !A!  # A€ # A€ # A€ # A€ A!  A!  A!  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A(À6 A/À;  :@ Aj"I @ k"E (AjA0  Aj!  Aj!  : A-A+ (: ("6@@ A H A! AK   A0: Aj! (!  A! @@@@@  6#" E  Aj$A!  (A l" (K   ǀ A;:  A! (Aj! (!(A! @@@@@  6 6  ( A n" mA0j: ("6  o" 6@ AK Aj!  #" E  Aj$A!  (Aj! ( (A n"o!(  ǀ A::  A!  A0j: Aj! 6@ -E (`- AqE /! (\! (! AA Aq  ܊ AAĀ" 6 E  ƀ A': A6< (`"/ " ; (<"6 A q ("A0F ( (j  (jk (AH AqAGrk" AH (X!    AAĀ" 6 ƀ A(: @ (AJ @ (X" (" (F Aj6 A-:   A- AAĀ" 6 ƀ A): @ (`/ " AqE @ (X" (" (F Aj6 A+:   A+ AAĀ" 6 ƀ A*: AqE @ (X" (" (F Aj6 A :   A  AAĀ" 6 ƀ A+:  (`" - A q (A0G ( ( (jk (j -AqAG (AHrk" AH (X! A0  AAĀ" 6 ƀ A,:  @ (?@ (6 #Aj" 6 (6  (6 (! A" A%6 A싀6 A틀6 6  A: A冀 A冀AĀ" 6 E  ƀ A: } @@ ̀AjJ (΀ 9 @@ ̀AjJ (΀ 9 (" (!  6 (! (!  k AAĀ" 6 ƀ A: { @@ ̀AjH (΀ 7 (! ( (E y (" -E y #Aj6 (" Au" s k6A! A!A! A! G @@ ̀AjG ( ΀ 6 (  ( ! V @@ ̀AjF ( ΀ 5 @@ ̀AjF ( ΀ 5 ( " (!  Y @@ ̀AjE ( ΀ 4 @@ ̀AjE ( ΀ 4 ( " (!  \ @@ ̀AjD ( ΀ 3 @@ ̀AjD ( ΀ 3 (  ] @@ ̀AjC ( ΀ 2 @@ ̀AjC ( ΀ 2 ( " (!  ^ @@ ̀AjB ( ΀ 1 @@ ̀AjB ( ΀ 1 ( " (!  ^ @@ ̀AjA ( ΀ 0 ( A! _ @@ ̀Aj@ ( ΀ / (  _ @@ ̀Aj? ( ΀ . (  ^ @@ ̀Aj> ( ΀ - (  ] @@ ̀Aj= ( ΀ , (  ] @@ ̀Aj< ( ΀ + (  ] @@ ̀Aj; ( ΀ * (  ] @@ ̀Aj: ( ΀ ) (  ] @@ ̀Aj9 ( ΀ ( (  ( ! H @@ ̀Aj8 ( ΀ ' (  ( ! G @@ ̀Aj7 ( ΀ & (  \ @@ ̀Aj6 ( ΀ % (  ] @@ ̀Aj5 ( ΀ $ (  ^ @@ ̀Aj4 ( ΀ # (  _ @@ ̀Aj3 ( ΀ " (  _ @@ ̀Aj2 ( ΀ ! (  ` @@ ̀Aj1 ( ΀ (  ` @@ ̀Aj0 A j!  ( ΀  A j!  @@ ̀Aj/ A j!  ( ΀  A j! ( ! ( ! ( ! - ! ( ! ( ! ( ! (@  jk AG AF   LqqqkAJ ( ! > ( ! ( ! ( ! - ! ( ! ( ! ( ! (!A(" A :% A6 A6 6  jk AG AF   Lqqqk6  A:$ A AAĀ" 6 ƀ A: ` @@ ̀Aj- ( ΀  (  ( ! < @@ ̀Aj, ( ΀  @@ ̀Aj, ( ΀  ( " (!  8 @@ ̀Aj+ ( ΀  @@ ̀Aj+ ( ΀  ( " (!  8 @@ ̀" AF AG  * ( ΀  (  @@ ̀" AF AG  ) ( ΀  (  @@ ̀Aj( ( ΀  @@ ̀Aj( ( ΀  ( " (!  . (Av! (! - ! ( ! ( ! ( !A ! A! > @@ ̀Aj' ( ΀  (  , @@ ̀Aj& ( ΀  (  ( ! 5 @@ ̀Aj% ( ΀  (  ) @@ ̀Aj$ ( ΀  (  ( ! 3 @@ ̀Aj# ( ΀  @@ ̀Aj# ( ΀  ( " (!  ( ! , @@ ̀Aj" ( ΀  @@ ̀Aj" ( ΀  ( " (!  ( ! + @@ ̀Aj! ( ΀  (  ( ! 0 @@ ̀Aj  ( ΀  (  ( ! / @@ ̀Aj ( ΀  (  ) @@ ̀Aj ( ΀ (  ( ! - @@ ̀Aj ( ΀ ( ! ( ! ( @ G ( ! - (! ( ! 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A还 (E  (" ("Av (lj!A!  @@ ̀Aj (,΀  @@ ̀Aj (,΀  (,"(! A!  # A р  Ȁ  A! @@@@@@@  6$ 6( 6 (! ( !   ! AĀ"6, E   ƀ A:4  60@  ( !  A! ($ AJkAM #"E  Aj$A!  (! ( ! ($! ((! (0!A还 (E  ( (j (( (0AJ"!  j  AJ"   kAvlj! ($ kAv!  ǀ A:4  A!  A! 6 Ȁ A6 A VA " 6 Aȋ6 Aɋ6  6  6  A: Aʋ   @@@@@@ - ("AN A!  # A A!  A! @@@@  6@ ( AtA|j"j(" ( j("F AA  K!  #"E  Aj$A!  @ ("AI Aj!A!  A!  ǀ A:  6 Ȁ A6 Aʋ HA0" 6 A􌀀6 A6  A:, A   @@@@@@@@@@@@@@@@ -, A!A- ( ("6A! E A!  @@ ̀"AF AG   ($΀  ($ @@ ̀Aj ((΀  @@ ̀Aj ((΀  (("(!   A! Ȁ  A<"Aóŀ6$ A6 A6 A6 A6 Aݽ€6  A:; A AAĀ"6$  ƀ A:, # A # A A!  A! @@@@@@@@@@@@  6 6 ("E   AtjAxj(   (! ( !  ( (Aj"AtjAxj(  6 AG  ("A6 ("6   (!  @ A G (" A8"A6 A6 B7  A:4 A AAĀ"6( E   ƀ A:, (" Aj6  AtjAj!  #"E  Aj$A!  #"E  Aj$A!  ǀ A:,  ǀ A:,  A! ( !  (6  6 A6 Aj! A6AA)B|7 6 Ȁ A6 A р VA(" 6 A6 A6  6  6  A:$ A   ~@@@@@@@@@@@@ -$ ( A<"Aŀ6$ A6 A6 A)6 A6 A€6  A:; A AAĀ"6  ƀ A:$  @@ ̀"AF AG  (΀ ( AAAHE A所 AڃAĀ"6  ƀ A:$  @@ ̀Aj  (΀  ( A0"Aπ6 A􌀀6 A6  A:, A AAĀ"6 E   ƀ A:$  @@ ̀Aj ( ΀  @@ ̀Aj ( ΀  ( "(!   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A @@ ̀Aj= (΀ 7 @@ ̀Aj= (΀ 7 ("(!  @ @@ ̀Aj< (΀ 6 @@ ̀Aj< (΀ 6 ("(!  ? @@ ̀Aj; (΀ 5 @@ ̀Aj; (΀ 5 ("(!  > @@ ̀Aj: (΀ 4 @@ ̀Aj: (΀ 4 ("(!  = @@ ̀Aj9 (΀ 3 @@ ̀Aj9 (΀ 3 ("(!  < @@ ̀Aj8 (΀ 2 @@ ̀Aj8 (΀ 2 ("(!  ; @@ ̀Aj7 (΀ 1 @@ ̀Aj7 (΀ 1 ("(!  : @@ ̀Aj6 (΀ 0 @@ ̀Aj6 (΀ 0 ("(!  9 @@ ̀Aj5 (΀ / @@ ̀Aj5 (΀ / ("(!  8 @@ ̀Aj4 (΀ . @@ ̀Aj4 (΀ . ("(!  7 @@ ̀Aj3 (΀ - @@ ̀Aj3 (΀ - ("(!  6 @@ ̀Aj2 (΀ , @@ ̀Aj2 (΀ , ("(!  5 @@ ̀Aj1 (΀ + @@ ̀Aj1 (΀ + ("(!  4 @@ ̀Aj0 (΀ * @@ ̀Aj0 (΀ * ("(!  3 @@ ̀Aj/ (΀ ) @@ ̀Aj/ (΀ ) ("(!  2 @@ ̀Aj. (΀ ( @@ ̀Aj. (΀ ( ("(!  1 @@ ̀Aj- (΀ ' @@ ̀Aj- (΀ ' ("(!  2 @@ ̀Aj, (΀ & @@ ̀Aj, (΀ & ("(!  1 @@ ̀Aj+ (΀ % @@ ̀Aj+ (΀ % ("(!  0 @@ ̀Aj* (΀ $ @@ ̀Aj* (΀ $ ("(!  / @@ ̀Aj) (΀ # @@ ̀Aj) (΀ # ("(!  . @@ ̀Aj( (΀ " @@ ̀Aj( (΀ " ("(!  - @@ ̀Aj' (΀ ! @@ ̀Aj' (΀ ! ("(!  , @@ ̀Aj& (΀ @@ ̀Aj& (΀ ("(!  + @@ ̀Aj% (΀  @@ ̀Aj% (΀  ("(!  * @@ ̀Aj$ (΀  @@ ̀Aj$ (΀  ("(!  ) @@ ̀Aj# (΀  @@ ̀Aj# (΀  ("(!  ( @@ ̀Aj" (΀  @@ ̀Aj" (΀  ("(!  ' @@ ̀Aj! (΀  @@ ̀Aj! (΀  ("(!  & @@ ̀Aj  (΀  @@ ̀Aj  (΀  ("(!  % @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  $ @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  # @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  " @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  ! @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   @@ ̀Aj (΀ @@ ̀Aj (΀ ("(!   @@ ̀Aj (΀ @@ ̀Aj (΀ ("(!   @@ ̀Aj (΀ @@ ̀Aj (΀ ("(!   @@ ̀Aj (΀ @@ ̀Aj (΀ ("(!   @@ ̀Aj (΀ @@ ̀Aj (΀ ("(!   @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!   @@ ̀Aj  (΀  @@ ̀Aj  (΀  ("(!   @@ ̀Aj  (΀  @@ ̀Aj  (΀  ("(!   @@ ̀Aj  (΀  @@ ̀Aj  (΀  ("(!   @@ ̀Aj  (΀  @@ ̀Aj  (΀  ("(!   @@ ̀Aj  (΀  @@ ̀Aj  (΀  ("(!   @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  @@ ̀Aj (΀  @@ ̀Aj (΀  ("(!  Ȁ  # A # A # A # A р A! A! A!  A!  A!  A!  A!  A! @@@@@@@@@@@@@@  6 6 6 6 6 ($"A򇀀G  ((!   ! A򇀀AĀ"6    AL  (! (!@ ( "E (   Aj!  j! (! (!   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  AF @ AG ((!   dž! AAĀ"6 E   ƀ A:  AF @ A؇G ((!   Ć! A؇AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A񆀀G ((!   ܅! A񆀀AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A‡G ((!   ! A‡AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AņG ((!   ʅ AņAĀ"6 E   ƀ A:  @ A놀G ((!   م! A놀AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A󈀀G ((!   ! A󈀀AĀ"6 E   ƀ A:  @ A샀G ((!   ! A샀AĀ"6 E   ƀ A:  @ AԃG ((!   ! AԃAĀ"6 E   ƀ A:  @ AԁG ((!   ! AԁAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A䉀G ((!   ! A䉀AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A牀G ((!   ! A牀AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AꊀG ((!   ! AꊀAĀ"6 E   ƀ A:  @ AG ((!   ֌ AAĀ"6 E   ƀ A:  @ AقG ((!   ߍ! AقAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG  ! AAĀ"6 E   ƀ A:  @ A܌G ((!   拀! A܌AĀ"6 E   ƀ A:  @ AG   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG   ((  @ AG   ((  AG   (( (! (!@ ( "E (   Aj!  j! (! (! 6 6 6 6@ E   ( ( j! @ A䂀G  !  @A| " @@ ($"A还J A|F  A鼳G A鼳 ($E ($!  ! AĀ"6 E   ƀ A:  @ A还F AG A ($E ($! ! AĀ"6 E   ƀ A:  A还 ($E ($!   ! AĀ"6 E   ƀ A:  A| ($E ($! ((!    ! AĀ"6 E   ƀ A:  ((!    ! AĀ"6   A!   ƀ A:  #"E  Aj$A!  ( ( j! (! (! (! (!  ǀ A: A! @@@@@@@@@@@@@@  6 6 6| 6x 6t (! (! ($"A򇀀G  ((!   ! A򇀀AĀ"6    AL  (Aj! (x" Aj! (t! (|!   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  AF @ AG ((!   dž! AAĀ"6 E   ƀ A:  AF @ A؇G ((!   Ć! A؇AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A񆀀G ((!   ܅! A񆀀AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A‡G ((!   ! A‡AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AņG ((!   ʅ AņAĀ"6 E   ƀ A:  @ A놀G ((!   م! A놀AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A󈀀G ((!   ! A󈀀AĀ"6 E   ƀ A:  @ A샀G ((!   ! A샀AĀ"6 E   ƀ A:  @ AԃG ((!   ! AԃAĀ"6 E   ƀ A:  @ AԁG ((!   ! AԁAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A䉀G ((!   ! A䉀AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ A牀G ((!   ! A牀AĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AꊀG ((!   ! AꊀAĀ"6 E   ƀ A:  @ AG ((!   ֌ AAĀ"6 E   ƀ A:  @ AقG ((!   ߍ! AقAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG  ! AAĀ"6 E   ƀ A:  @ A܌G ((!   拀! A܌AĀ"6 E   ƀ A:  @ AG   ! AAĀ"6 E   ƀ A:  @ AG ((!   ! AAĀ"6 E   ƀ A:  @ AG   ((  @ AG   ((  AG   (( (|Aj! (t" Aj! (x! (! 6 6 6 6 (" (6@ E   Aj! @ A䂀G  !  @A| " @@ ($"A还J A|F  A鼳G A鼳 ($E ($!  ! AĀ"6 E   ƀ A:  @ A还F AG A ($E ($! ! AĀ"6 E   ƀ A:  A还 ($E ($!   ! AĀ"6 E   ƀ A:  A| ($E ($! ((!    ! AĀ"6 E   ƀ A:  ((!    ! AĀ"6   A!   ƀ A: #"E  Aj$A!  (Aj! (! (! (! (!  ǀ A: A! @@@@@@@@@@@@@@  6\ 6` 6X 6T 6P ($"A򇀀G  ((! ! A򇀀AĀ"6    AL  (`Aj! (T"Aj! (P! (X!   ƀ A0:  @ AG ((! ! AAĀ"6 E   ƀ A1:  AF @ AG ((! dž! AAĀ"6 E   ƀ A2:  AF @ A؇G ((! Ć! A؇AĀ"6 E   ƀ A3:  @ AG ((! ! AAĀ"6 E   ƀ A4:  @ AG ((! ! AAĀ"6 E   ƀ A5:  @ A񆀀G ((! ܅! A񆀀AĀ"6 E   ƀ A6:  @ AG ((! ! AAĀ"6 E   ƀ A7:  @ A‡G ((! ! A‡AĀ"6 E   ƀ A8:  @ AG ((! ! AAĀ"6 E   ƀ A9:  @ AņG ((! ʅ AņAĀ"6 E   ƀ A::  @ A놀G ((! م! A놀AĀ"6 E   ƀ A;:  @ AG ((! ! AAĀ"6 E   ƀ A<:  @ AG ((! ! AAĀ"6 E   ƀ A=:  @ AG ((! ! AAĀ"6 E   ƀ A>:  @ AG ((! ! AAĀ"6 E   ƀ A?:  @ A󈀀G ((! ! A󈀀AĀ"6 E   ƀ A:  @ A샀G ((! ! A샀AĀ"6 E   ƀ A:  @ AԃG ((! ! AԃAĀ"6 E   ƀ A:  @ AԁG ((! ! AԁAĀ"6 E   ƀ A:  @ AG ((! ! AAĀ"6 E   ƀ A:  @ A䉀G ((! ! A䉀AĀ"6 E   ƀ A:  @ AG ((! ! AAĀ"6 E   ƀ A:  @ A牀G ((! ! A牀AĀ"6 E   ƀ A:  @ AG ((! ! AAĀ"6 E   ƀ A:  @ AꊀG ((! ! AꊀAĀ"6 E   ƀ A:  @ AG ((! ֌ AAĀ"6 E   ƀ A:  @ AقG ((! ߍ! AقAĀ"6 E   ƀ A:  @ AG ((! ! AAĀ"6 E   ƀ A:  @ AG ((! ! AAĀ"6 E   ƀ A:  @ AG  ! AAĀ"6 E   ƀ A:  @ A܌G ((! 拀! A܌AĀ"6 E   ƀ A:  @ AG  ! AAĀ"6 E   ƀ A:  @ AG ((! ! AAĀ"6 E   ƀ A:  @ AG ((  @ AG ((  AG  (( (XAj! (P"Aj! (T! (`! 6l 6p 6h 6d (\" )7@ E   Aj! @ A䂀G !  @A| " @@ ($"A还J A|F  A鼳G A鼳 ($E ($! ! AĀ"6 E   ƀ A-:  @ A还F AG A ($E ($! ! AĀ"6 E   ƀ A,:  A还 ($E ($! ! AĀ"6 E   ƀ A.:  A| ($E ($! ((!  ! AĀ"6 E   ƀ A/:  ((!  ! AĀ"6   A!   ƀ A+: #"E  Aj$A!  (\Aj! (d! (h! (l! (p!  ǀ A: A! @@@@@@@@@@@@@@  68 6< 64 60 6, ($"A򇀀G  ((!  ! A򇀀AĀ"6    AL  (?@ABCDEFGHIJKLMNOPQRST ((!A!A!@ (E A!A! (," -AjAqAI (("A -"! A ! 6 6 ($"6A" 6 A6 A6  A: A AAĀ"6 E   ƀ A:  @@ ̀Aj{ (΀ 2 @@ ̀Aj{ (΀ 2 ("(!   A<" Aŀ6$ A6 A6 A6 A€6 AÀ6  A:; A AAĀ" 6 ƀ A:  @@ ̀" AF AG  z (΀ 1 ( 6 B7 ((4"6  (" ,"Atj-A q t Aj! x @@ ̀Ajx ( ΀ / @@ ̀Ajx ( ΀ / ( "(!  } @@ ̀Ajw ( ΀ . @@ ̀Ajw ( ΀ . ( "(!  } @@ ̀Ajv ( ΀ - @@ ̀Ajv ( ΀ - ( "(!   @@ ̀Aju ( ΀ , @@ ̀Aju ( ΀ , ( " +!   @@ ̀Ajt ( ΀ + @@ ̀Ajt ( ΀ + ( "(!   @@ ̀Ajs ( ΀ * @@ ̀Ajs ( ΀ * ( "(!   @@ ̀" AF AG  r ( ΀ ) (  @@ ̀" AF AG  q ( ΀ ( (  @@ ̀" AF AG  p ( ΀ ' (  @@ ̀" AF AG  o ( ΀ & (  @@ ̀" AF AG  n ( ΀ % (  @@ ̀" AF AG  m ( ΀ $ (  @@ ̀Ajl ( ΀ # @@ ̀Ajl ( ΀ # ( " +!   @@ ̀Ajk ( ΀ " @@ ̀Ajk ( ΀ " ( " +!   @@ ̀Ajj ( ΀ ! @@ ̀Ajj ( ΀ ! ( "(!   @@ ̀Aji ( ΀ @@ ̀Aji A j!  ( ΀  A j!  @@ ̀Ajh ( ΀  @@ ̀Ajh A j!  ( ΀  A j! ("(! A~A} ! A!  @@ ̀Ajf ( ΀  @@ ̀Ajf ( ΀  ( " +!   @@ ̀Aje ( ΀  @@ ̀Aje ( ΀  (   @@ ̀" AF AG  d ( ΀  (  @@ ̀Ajc ( ΀  @@ ̀Ajc ( ΀  ( "(!   @@ ̀Ajb ( ΀  @@ ̀Ajb ( ΀  ( " +!   @@ ̀" AF AG  a ( ΀  (  @@ ̀" AF AG  ` ( ΀  (  @@ ̀" AF AG  _ ( ΀  (  @@ ̀" AF AG  ^ ( ΀  (  @@ ̀Aj] ( ΀  @@ ̀Aj] ( ΀  ( "(! A~A} !A!  @@ ̀Aj\ ( ΀  @@ ̀Aj\ ( ΀  (   @@ ̀Aj[ ( ΀  @@ ̀Aj[ ( ΀  (   @@ ̀AjZ ( ΀  @@ ̀AjZ ( ΀  ( "(!   @@ ̀" AF AG  Y ( ΀  (  @@ ̀AjX ( ΀  @@ ̀AjX ( ΀  (   @@ ̀AjW ( ΀  @@ ̀AjW ( ΀  ( " +!   @@ ̀AjV ( ΀ @@ ̀AjV ( ΀ (   @@ ̀AjU ( ΀ @@ ̀AjU ( ΀ (   @@ ̀AjT ( ΀ @@ ̀AjT ( ΀ ( " +!   @@ ̀AjS ( ΀ @@ ̀AjS ( ΀ ( "(!   @@ ̀" AF AG  R ( ΀ (  @@ ̀AjQ ( ΀  @@ ̀AjQ ( ΀  (   @@ ̀AjP ( ΀  @@ ̀AjP ( ΀  ( A5 ( "k! ( ( kAt j! !  @@ ̀" AF AG  O ( ΀  (  @@ ̀AjN ( ΀  @@ ̀AjN ( ΀  ( "(! A!  @@ ̀AjM ( ΀  @@ ̀AjM ( ΀  ( "(!   ?AÀA€A Aŀς AAĀ" 6 ƀ A.:  @@ ̀" AF AG  L ( ΀  (  @@ ̀AjK (΀  @@ ̀AjK (΀  (  @@ ̀AjJ (΀  @@ ̀AjJ (΀  (" +!   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(" Aj!> -APjAqA O   ǀ A1:  A! @ (" *!  >6 *! 8 Ȁ A6 Aȍ oA" 6, A̍6 A͍6  6(  6$  6  7  6  A:H AˍC  ~}#Ak"$@@@@@@@@@@@@@@@ -H )"BU @ B~V #AjA"6CC ( ! ( !@ B~R (! A6A!  ("60A4"A "k6 Aˋ6 A̋6 A6  6  6  A:0 A͋ A͋AĀ"64  A k!  @@ ̀Aj  (4΀  @@ ̀Aj  (4΀  (4A (k! (0! @ A t"q" ($" ((" vAq (,r A tAsqAGr"r Aj q B!A!A!  #AjA"6 A6 Aj! B!  BU A (("t" ($"q! (,! 6< 6@ 68 7 E  Aj q ( "("Aqr rE   Aj"6@ Aq BR BB Aq!  ( !A4"Aˋ6 A̋6 B7  6  6  A:0 A͋ A͋AĀ"6D E   ƀ A:H  @@ ̀Aj (D΀  @@ ̀Aj (D΀  (D )! ( " (Ar6 BU  )B|! @AA (?@ABCDEFGHIJKLMNOPQRS (m(!A!A! @ (mE A!A! (," -AjAqAI (("A -"! A ! 6m 6m ($"6mA" 6 A6 A6  A: A AAĀ"6m E   ƀ A:r  @@ ̀Ajz (m΀ 1 @@ ̀Ajz (m΀ 1 (m"(!   A<" Aŀ6$ A6 A6 A6 A€6 AÀ6  A:; A AAĀ" 6m ƀ A:r  @@ ̀" AF AG  y (m΀ 0 (m 6m B7 (m(4"6m  (m" ,"Atj-A q s Aj! w @@ ̀Ajw (m΀ . @@ ̀Ajw (m΀ . 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A~A} !A!  @@ ̀Aj[ (p΀  @@ ̀Aj[ (p΀  (p  @@ ̀AjZ (p΀  @@ ̀AjZ (p΀  (p  @@ ̀AjY (p΀  @@ ̀AjY (p΀  (p"(!   @@ ̀" AF AG  X (p΀  (p @@ ̀AjW (q΀  @@ ̀AjW (q΀  (q  @@ ̀AjV (q΀ @@ ̀AjV (q΀ (q" )! )!   @@ ̀AjU (q΀ @@ ̀AjU (q΀ (q  @@ ̀AjT (q΀ @@ ̀AjT (q΀ (q  @@ ̀AjS (q΀ @@ ̀AjS (q΀ (q" )! )!   @@ ̀AjR (q΀ @@ ̀AjR (q΀ (q"(!   @@ ̀AjQ (q΀  @@ ̀AjQ (q΀  (q  @@ ̀AjP (q΀  @@ ̀AjP (q΀  (qA (p" k! (p (qkAt j! !  @@ ̀" AF AG  O (r΀  (r @@ ̀AjN (r΀  @@ ̀AjN (r΀  (r"(! A!  @@ ̀AjM (r΀  @@ ̀AjM (r΀  (r"(!   ?AÀA€A Aŀς AAĀ" 6r ƀ A-:r  @@ ̀" AF AG  L (r΀  (r @@ ̀AjK (r΀  @@ ̀AjK (r΀  (r  @@ ̀AjJ (r΀  @@ ̀AjJ (r΀  (r" )! )!   Ȁ   # "A # %A # (A # :A # 'A # 9A # &A # &A # 7A # 7A # &A # &A # /A # 4A # .A # 3A # )A # %A # %A # %A # !A # A # A # A # A # A # A # A # A # A # A # A # A # #A A! & A! 9 A! 6 A! 5 A! 8 A! < A! ; A! < A! ? A! @ A! B A! F A! E A! F A! E A!  A!  A! G A! U A! w A! T A! c A! ` A! _ A! _ A! f A! e A! d A! { A! 1 A! < A! n A! b A! [ A!  A! @@@@@  6r#"E  Aj$A!  (r"Aj! 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(pAt" jA6 9AJ   j!;A! @@@@@@@@@@@@@@@  ;(! 96r -7mA! (q"F @ Av" n" lkAt  (pAtjA|j("Avr"  Aq"l"O Aj!@ j" O !  @ I !  j! A~j! @ k" n" lkAt Aqr" l"O Aj!@ j" O !  @ I !  j! A~j! k! 5q Atr"~" ! B !  @  (p"Atj( G (r!  A<" 6 A񌀀6 A򌀀6  6  6  6  A:8 A󌀀 A󌀀AĀ"6r E  ƀ A,:r ( (rAj! 6r  (p"Atj" A|j(" 6r 6@ AH (pAtA|j"E A$j   A6 @@ (r" A6l 6lA g"k! )m }!  AJ  )! (6l 7l 6l )m! 7m 6r#"E  Aj$A! Aj!; (rA j!9 )m!-  @ AG )m!-A!   AA k AċAĀ" 6r E ƀ A.:r $ ǀ A=:r # (rAj! (q (rj! (r" (q"k! (r Ik! 6r 6r 6r 6r@ K G   (pAtjAxj(M   (qAsM  Aj! 6r (p!A0" 6 A6 A6 Aj6 6 6  A:, A AAĀ"6r E   ƀ A+:r @#"E Aj$A!  ǀ A?:r  A!  A!  A! (r" (r" Ajv (lr6lA k! )m!- 6r 6r -7lA! (p":r  A! (r! )l! (l! (n! 4l! 5o!# (m! (r!  A0j  B| A k    j| #Sr AڍAĀ" 6r@ B! B!  ƀ A/:r  (q" (q" Ajv (lr6l Aj! )l! (q! (q! (l! (n! 4l! 5o!# (m! Aj  B|   Aj rAG   j| #Sr AڍAĀ" 6q E  ƀ A&:r  (qAt (qr (p" Ajv (lr6l Aj! (p! (p! (q! (q! (l! (n! 4l! 5o! )l!# (q! (q! (m! Aj  #B|   Atr   j| S   Av" n Aq" lk n lGr AڍAĀ" 6q E  ƀ A#:r  (oAt (okAj"AvkAJ  Atj( v6l A! ( A!=A! @@@@@  =6r#" E  Aj$A!   (r" Atj(  Aj!=  ǀ A:r  A! (l! (n! (o!  (oAt (ok"Aj"Av Aq"Ek"Atj(! (m! Aj  Aj   AjA  j I Hr AڍAĀ" 6p E ƀ A:r  &Aj! &-" A0G A! @@@@@  6r#" E  Aj$A!  (r" Aj! -" A0G   ǀ A::r  A! !@@ APjAqA K APj!  (m(8 Atj(Aj! At(̀"6o@ AљÀA€AAŀς AAĀ" 6o ƀ A :r A kt6l ! 5n!@@ )l"#BU B }B!$  B # |}B!$ @ $ Z AŀA€AAŀς AAĀ" 6o ƀ A:r #| B|B{|7A!> (oAj"?E A k!@A! @@@@@@  6o @6o ?6o (o ,Atj/" ;r@ A (m A qj","APj" AqA M (m(8 Atj(Aj! 6o@@ @AH  >Atj" ( @A}jtr6 @A|j!   >Atj" ( A @kvr6@ > ?Aj"AE  Aj"B-A0F A!  >Aj">Atj @Ajt6 @Aj! 6o >6o ?AF #" E  Aj$A!  (oAj!? (oA (m -rAqjAj! (o!@ (o!>  ǀ A;:r  A! A! @@@@@  B6o A6o AAF #" E  Aj$A!  A! (o" -A0G  Aj!B (oAj!A  ǀ A<:r A! A! 5n! (o! )l! (o! (o! (m!  A j   Aj| B|B||  AjtA  AڍAĀ" 6o E  ƀ A:r  >E  >At" E A 5n! (o! )l! (m! Aj   Aj| B|B|| AAA AڍAĀ" 6o E  ƀ A:r  @@ (nAG B! BB -rA-F!  #AjA"6 -r! @ -sA-G B! BB AqA-F!  B@B AqA-F!B! 7l 7l !Aj!C !-APjAqA O A! @@@@@  C6r#" E  Aj$A!  (r" Aj!C -APjAqA O   ǀ A4:r  A! @ (m" E C6 )l! )l!  B!B! 7 7 Ȁ A6 A׍ Aj$ xA" 68 Aۍ6 A܍6  64  60  6,  6(  7  A:` Aڍ B7 B7  ~#Ak"$@@@@@@@@@@@@@@@@@@@@ -` )"BU @ B~V #AjA"6B!BB (,!  (8 (0A (4tAsqAGr!@ B~R (("(! (! B7 ( ! (! B7   rrAGr!A!  A "k! ((! B~V  A k" Av"Atj("6<@ E !@  (AGr! Aj! Aj" 6@ Av!@ Aq" A!    A Aq"tAsqAGr!     AtjA k Ќ A͋AĀ"6D E   ƀ A:`  @@ ̀Aj (D΀ @@ ̀Aj (D΀ (D )"B~T A k"Aq! (@ (<"A tAsqAGr!  At!A kAqAt!@ (( j"  j(6  Aj"G @A (kAv"At"E ((A kAtjA  A (k"Aq! (@ (<"A tAsqAGr!  ("6HA4" 6 Aˋ6 A̋6 A6  6  6  A:0 A͋ A͋AĀ"6L  A k!  @@ ̀Aj  (L΀  @@ ̀Aj  (L΀  (LA (k! (8 (0A (4tAsqAGr! (H! @ A t"q" (0 (4vAq r"r Aj q B!A!A!  #AjA"6 B7 B7B!  BU A (4"t" (0"q! (8! 6T 6X 6P 7 E  Aj q (("("Aqr rE   Aj"6@  ((" (Aj"6  ((Aj" (Aj"6  ((A j" (Aj6 @ (("( "Aq BR BB Aq!  A4"Aˋ6 A̋6 B7  6  6  A:0 A͋ A͋AĀ"6\ E   ƀ A:`  @@ ̀Aj (\΀  @@ ̀Aj (\΀  (\ ) ! ((" ( Ar6 BU  ) B|! @AA (Tkv (Pq (XrE B?7 B7 (("/ (,At AtAjAqrrB )"B ! B 5!  Ȁ    ƀ A:`  р #AjA"6B@B (,!B! 7 7 Ȁ A6 Aڍ Aj$ sA" 6$ Aݍ6 Aލ6  6  6  6  6  6  6  A:t Aٍ    ~@@@@@@@@@@@@@@@@@@@@@@@@@@ -t  (!A! (A6 AH ( ! (!A!A!  @@ ̀"AF AG   ((΀  (( @@ ̀Aj (8΀  @@ ̀Aj (8΀  (8"(! A!  @@ ̀"AF AG   (H΀  (H @@ ̀Aj (`΀  @@ ̀Aj (`΀  (`"(!   ̀"AF  AG  р (p΀  (p Ȁ  A<"Aŀ6$ A6 A6 A6 A€6 AÀ6  A:; A AAĀ"6(  ƀ A:t  # AۂÀ # AۂÀ # AۂÀ # AۂÀ A!  A!  A!  A!  @@@@@@@@@@@@@@@@@@@@  60 64 6, A G  (!@ (("  6A!  A4"A6 Aҋ6 AӋ6  6  6  6  A:0 A΋ A΋AĀ"68 E   ƀ A:t  6< ((! (" (" (0j" 6A! O A! Aj"E  Aj!  (XAj! (LAj! (,Aj! ,v (PA ljAPj!  -u (4 (TAj"j-F  ( !  A! (@Aj"E  Aj! 6@ (Aj"6D  (Aj"6A! E  A!A! (< j"E @ ("("A H A<"Aŀ6$ A6 A6 A6 A€6 A€6  A:; A AAĀ"6H  ƀ A:t  ( Atj 6 (Aj! ( 6A!A! 6L 6P (4"-"AFjAqAK @ ($" ( !  @ Aq -F ( !  A! -" E A! -F ( !  6T ($ Aj"j-":u   (4 j"-! :v 6X@ (,AJ (L"Aj!  (PA ljAPj!@@ (")" BS A kU B7 AtÀj" Atj(! ( l!  AtÀj(! 6\ (!@ ("("  6 A6  A4" 6 Aҋ6 AӋ6  6  6  6  A:0 A΋ A΋AĀ"6` E  ƀ A:t  #"E  Aj$A!  #"E  Aj$A!  #"E  Aj$A!  ǀ A:t ǀ A :t ǀ A:t  A!  A! 6d ((! (" (" (\j"6  O @ Aj"E Aj! A!  A!  @@@@@  6h (Aj"6l  (Aj"6  #"E  Aj$A!  @ (hAj" A!  Aj!  ǀ A:t  A! A! (d j"E @ ("("A H A<"Aŀ6$ A6 A6 A6 A€6 A€6  A:; A AAĀ"6p  ƀ A:t  (!  Aj6  Atj 6 (XAj6 Ȁ A6 Aٍ cA" :5 Aߍ6 A6  6  6  A:4 A؍ B7 B7  ~ Aj!@@@@@@@@@@ -4 ( !A!  @@@ ̀Aj (0΀  @@ ̀Aj (0΀  (0")!   Ȁ  # A р A! @@@@@@  6$@ -"APjAqA I AjAqAI AqAF AjAqAK  #"E  Aj$A!  ($Aj!  @ Aq -5F B!  #Aj"6( (6, ( !A"A: À60 AÍ6 Ač6 B7(  6$  6  A: Aō AōAĀ"60@  !   ƀ A:4  ǀ A:4  A! ($! (( (,6B!  (F  B! @ ( "E  ($6 7 7 Ȁ A6 A؍ lA" :}  6 Aҍ6 AӍ6  6  6  6  6  A:| Aԍ   ~@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -|   A!@@ ( A!  A! (("(,"-AjAqAI (("A -"! A ! 6 6$ ("A$K AF ((4"6(  ( ","Atj-A q   @@ ̀Aj  (0΀  @@ ̀Aj  (0΀  (0"(!   @@ ̀Aj  (D΀  @@ ̀Aj  (D΀  (D"(!  (, -~"A-F A+Frj!  Ȁ  # A # A # A # A # A # A р #AjA6A!  A! A! A! A!  A!  A!  A! @@@@@  6x#"E  Aj$A!  (x"Aj! (( ,"Atj-A qE   ǀ A:|  A! 6, :~@  ( !   A-F A+Frj"-": (!@@ A0G @@  ,AtÀj(AG Aj!A!A!  @ -}E @   A! ,AtÀj(AG Aj!  A!A!     @ ( A!A !  ($! ܍! AAĀ"60 E  ƀ A:|  64 (,! -~!@   Aq"A-F A+Frj!A! A! ($-  Aq"A-F A+Frj-G A!  (! A! A!  @@@@@  68@ Aj (4"G (, -~"A-F A+Frj! #"E  Aj$A!  ($ (8Aj"j- (, -~"A-F A+Frj j-F   ǀ A:| A! (, -~"A-F A+Frj! -"E A! @@@@@@@@@@@@@  : 6< AFjAqAK A! ($- -G   (ar_ptr == avretry_cpu:%s=%llu:%s=%luhhuThuarm_ac57::CPU_CYCLES:uperf::CYCLES:ustatus-word=%u__dcigettextConnection timed outAuguste != ESRCH || !robustNo route to host_nl_make_l10nflistcorrupted double-linked listL1 data cache prefetch requestL2 data prefetch requestdata.__outbuf != (unsigned char *) dstqsort_r_mergesortExceptions taken, instruction abortException taken, instruction abortSoftware caused connection abortglibc: assert__wasm32_signal_dispatch_restartCPU partInvalid slotNo operation sent for execution on a slot__sched_cpucountE04-pmu-count%s-countLevel 1 instruction cache miss due to prefetch access countAccesses to the data TLB that caused a page walk. Counts any data access which causes L2D_TLB_REFILL to countAccesses to the instruction TLB that caused a page walk. Counts any instruction which causes L2D_TLB_REFILL to counttracepointperf_eventpfmlib_sanitize_eventpfmlib_parse_eventperf_table_alloc_eventE05-pmu-presentInvalid argumentAccess with additional latency from alignmentStore with additional latency from alignmentLoad with additional latency from alignmentAccesses with additonal latency from aligmentStores with additonal latency from aligmentLoads with additonal latency from aligmentFor odd-numbered counters, this event increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no incrementInstruction architecturally executed, Condition code check pass, software incrementInstruction architecturally executed (condition check pass) software incrementInstruction architecturally executed (condition check pass) Software incrementmap->l_tls_modid == total + cntlongjmp while a longjmp is in transitexception raised while an exception is in transitPE Trace Unit external output 3 This event is not exported to the trace unitPE Trace Unit external output 2 This event is not exported to the trace unitPE Trace Unit external output 1 This event is not exported to the trace unitPE Trace Unit external output 0 This event is not exported to the trace unit_dl_allocate_tls_init_IO_stdfiles_init__grouping_iterator_initpfm_perf_init__ptmalloc_initBranch Prediction UnitRead requests to LLC which hitPage Walk Cache level-2 stage-2 hitPage Walk Cache level-1 stage-2 hitPage Walk Cache level-2 stage-1 hitPage Walk Cache level-1 stage-1 hitPage Walk Cache level-0 stage-1 hithack_digit__lll_lock_wait__mpn_rshift__mpn_lshiftdlmopen into a new namespace not supported on wasm32-hwjs yetdlopen(NULL) (main-program handle) not supported on wasm32-hwjs yet__wmemset_dl_determine_tlsoffsetNetwork dropped connection on resetLevel 3 reset_nl_normalize_codesetISO/IEC 14652 i18n FDCC-setSocket operation on non-socketProtocol wrong type for socketNumber of accesses to another socketpfmlib_check_structto_inpunctMarvell ThunderX2 node 1 Cross-Socket InterconnectMarvell ThunderX2 node 0 Cross-Socket Interconnect_dl_addr_inside_objectwasm32-hwjs dlopen: host failed to stage/instantiate the shared objectOct/proc/statBad font file formatSatException taken, other synchronouspfmlib_init_pmusFile existsslots/proc/mountsE08-ac57-neventsadd_optional_events/tracing/eventspfm_perf_add_defaultsScu hwpf ld requests that missL1 data cache late missITB missDTB missOperation already in progressOperation now in progressNo such device or addressCannot assign requested addressBad addressNo such processspill_successE30-strerror-successSuccessNode memory accessChecked data memory accessData memory accesshit accessBus accessmiss accessBus peripheral accessBus not normal accessBus normal accessprefetch accessexclusive accessData memory write accessBus write accessLevel 2 data cache write accessLevel 1 data cache write accessLevel 1 instruction cache accessLevel 2 data cache accessLevel 1 data cache accessUnaligned accessData memory read accessBus read accessLevel 2 data cache read accessLevel 1 data cache read accessUnaligned read accessInstruction TLB accessLevel 1 data TLB accessAttributable memory read operation or attributable memory write operation that causes a TLB accessChecked data memory acessChecked data memory write acessChecked data memory read acessProcedure return, instruction architecturally executed, condition check passWrite to CONTEXTIDR, instruction architecturally executed, condition check passSoftware change of the PC, instruction architecturally executed, condition check passExclusive operation speculative executed - Store exclusive passExclusive operations speculative executed - STREX or STX passExclusive operation speculative executed - STREX or STX passpfmlib_build_event_pattrspfmlib_compact_pattrspfm_arm_perf_validate_pattrspfm_perf_perf_validate_pattrspfm_arm_get_event_nattrsperf_get_os_nattrs__call_tls_dtorsLocal memory errorspin event to countersFor odd-numbered counters, this event increments the count by one for each overflow of the preceding even-numbered counter. There is no increment for even-numbered countersinvalid parametersToo many users__run_exit_handlersMemory data transfersExternal mmu tlbi cacheopsInternal mmu tlbi cacheopsCounts the number of speculatively executed micro-ops/proc/self/mapspfmlib_init_osAttributable L3 cache refill This event counts for any cacheable read transaction returning data from the SCU for which the data source was outside the cluster. Transactions such as ReadUnique are counted as read transactions, even though they can be generated by store instructionsMemory write transactionsMemory read transactionsLevel 2 data cache invalidationsLevel 1 data cache invalidations__wctransns == l->l_nsLevel 2 data cache write refillsLevel 1 data cache write refillsLevel 1 data TLB write refillsLevel 1 instruction cache refillsLevel 2 data cache refillsLevel 1 data cache refillsLevel 2 data cache read refillsLevel 1 data cache read refillsLevel 1 data TLB read refillsLevel 1 instruction TLB refillsLevel 1 data TLB refillsNo operation sent due to the backend and memory stallsfree(): corrupted unsorted chunksmalloc(): corrupted unsorted chunksToo many linksToo many levels of symbolic linkspfmlib_pmu_sanity_checksLevel 2 data cache cleaning and coherency write-backsLevel 2 data cache victim write-backsLevel 2 data cache write-backsLevel 1 data cache write-backsdebugfsA Load hit store forwarding. Load completesCounts the number Level 1 data cache long-latency missesCounts L1 instruction cache long latency missesCounts L3 cache long latency missesCounts L2 cache long latency missesLast level cache prefetch missesL1I cache prefetch missesL1 cache prefetch missesData TLB prefetch missesNode prefetch missesLast level cache store missesL1 cache store missesData TLB store missesNode store missesLast level cache load missesL1I cache load missesL1 cache load missesInstruction TLB load missesData TLB load missesBranch load missesNode load missesNo child processesData memory accessesLast level cache prefetch accessesL1I cache prefetch accessesL1 cache prefetch accessesData TLB prefetch accessesNode prefetch accessesData memory write accessesBus write accessesLevel 2 data cache write accessesLevel 1 data cache write accessesUnaligned write accessesLevel 1 data TLB write accessesLast level cache store accessesL1 cache store accessesData TLB store accessesNode store accessesLevel 1 instruction cache accessesLevel 2 data cache accessesLevel 1 data cache accessesUnaligned accessesLast level cache load accessesL1I cache load accessesL1 cache load accessesInstruction TLB load accessesData TLB load accessesBranch load accessesNode load accessesData memory read accessesBus read accessesLevel 2 data cache read accessesLevel 1 data cache read accessesUnaligned read accessesLevel 1 data TLB read accessesInstruction TLB accessesLevel 1 data TLB accessesBus access This event counts for every beat of data transferred over the data channels between the core and the Snoop Control Unit (SCU). If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD, BUS_ACCESS_WR, and any snoop data responsesgconv-modulesToo many open filesConstant frequency cyclesInstruction fetch stall cyclesBus cycles. This event duplicate cyclesCyclesAttempting to link in too many shared librarieserror while loading shared libraries/sys/kernel/mm/hugepagesOut of streams resourcesLast Level cache misses for readsLast Level cache accesses for readsL3 cache reads__wcsrtombs_nl_expand_alias/locale.aliasLocal memory error This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs%s::%s/sys/devices/%s/events/%s%s/%sflux_wrpfmlib_parse_event_attrpfmlib_getcpuinfo_attrE23-badattr-is-attrE32-strerror-attrstrstr%s-fstrfile->wide_stream._IO_write_ptr >= file->next->write_ptrfile->stream._IO_write_ptr >= file->next->write_ptroutbuf == outerrAprInvalid request descriptorBad file descriptormonitor in hypervisorLocal memory errorInput/output errorSrmount errorExec format errorProtocol errorAdvertise errorMemory page has hardware errorStreams pipe errorRFS specific errorRemote I/O errorExceptions taken locally, data abort or SErrorException taken, data abort or SErrorE03-version-minorE02-version-major__memrchr__wmemchr__memchrrx_outerLevel 1 data cache refill, outerLevel 1 data cache refills, inner. Counts any L1D cache line fill which hits in the L2, L3 or another core in the clusterAttributable L3 unified cache refills. Counts any cacheable read transaction returning data from the SCU for which the data source was outside the clusterLevel 1 data cache refills, outer. Counts any L1D cache line fill which does not hit in the L2, L3 or another core in the cluster and instead obtains data from outside the clusterFor odd-numbered counters, increments the count by one for each overflow of the proceeding even countermunmap_chunk(): invalid pointermremap_chunk(): invalid pointerfree(): invalid pointerrealloc(): invalid pointerCPU implementerinvalid mode parameterInvalid or incomplete multibyte or wide characterLevel 1 data cache refill, innerE11-modifierScu ld/st requests that hit cache or msg for lines brought in by the hardware prefetcherOperation counted by ASE_SVE_INT_SPEC where the largest type is 8-bit integerOperations counted by ASE_SVE_INT_SPEC where the large type is a 8-bit integerOperation counted by ASE_SVE_INT_SPEC where the largest type is 16-bit integerOperations counted by ASE_SVE_INT_SPEC where the large type is a 16-bit integerOperation counted by ASE_SVE_INT_SPEC where the largest type is 64-bit integerOperations counted by ASE_SVE_INT_SPEC where the large type is a 64-bit integerOperation counted by ASE_SVE_INT_SPEC where the largest type is 32-bit integerOperations counted by ASE_SVE_INT_SPEC where the large type is a 32-bit integer__printf_fphex_buffer__wprintf_fphex_l_buffer__wprintf_buffer__printf_bufferNumber of times SPE completed sample record passes the SPE filters and is written to the bufferInstruction Translation Lookaside BufferData Translation Lookaside Buffer__libc_cleanup_push_deferConnection reset by peerOctobergroup_numberNovemberSeptemberDecemberMar__qsort_rCross-trigger interface output trigger rException taken, irqException taken, fiqfreq_IO_cleanupsave_for_wbackupsave_for_backuppfmlib_perf_encode_tpprefetch_dropindirect_msort_with_tmpstrcmpstrncmpmemcmp__strcasecmp__strncasecmp__mpn_cmp__printf_buffer_flush_fpSepsysmalloc_mmap%I:%M:%S %pincr <= powers->p_expodig_no >= int_nollohho/proc/cpuinfo/proc/meminfopfm_get_pmu_infopfm_get_event_infopfm_arm_get_event_attr_infoperf_get_os_attr_info_IO_getline_infoCannot send after transport endpoint shutdownHost is downNetwork is downSunJun_IO_wdefault_xsputn_IO_default_xsputn_IO_wfile_xsputn_IO_new_file_xsputn_IO_wdefault_xsgetn_IO_default_xsgetn_IO_file_xsgetnInstruction architecturally executed, Condition code check pass, exception returnInstructions architecturally executed (condition check pass) - Exception returnInstruction architecturally executed (condition check pass) - Exception returnInstruction architecturally executed (condition check pass) Exception returnInstruction architecturally executed (condition check pass) - procedure returnInstruction architecturally executed, Condition code check pass, procedure returnBranch speculatively executed, returnstrspnstrcspnstr_to_mpn__add_to_environmonitor host executionmonitor guest executionCounts cycles in which no operation is sent for executionOperation speculatively executed, floating point instructionOperation speculatively executed, Cryptographic instructionNumber of cycles in which CPU is in low power mode due to WFI/WFE instructionOperation speculatively executed, Advanced SIMD instructionBTB mispredictionISO/IEC JTC1/SC22/WG20 - internationalizationfind_derivationMon_IO_adjust_column_nl_find_domain_nl_load_domainNumerical argument out of domain__libc_start_call_mainE10-plain__new_exitfnKeld Simonsen_IO_new_file_fopen__gconv_open_dl_open__wcslen_dl_strlen_dl_debug_strlen__strlenExceptions takenException taken__strtof_nan__strtod_nan__strtold_nanJan__mpn_impn_mul_n__mpn_add_n__mpn_sub_nrx_ops_numvictim_numspill_numwasm32_sentinel_num__gconv_close_transformpfm_perf_pmu_supported_plmLevel 2 data cache writeback victimLevel 1 data cache writeback victimLevel 2 data cache write-back, victimLevel 1 data cache write-back, victim_int_free_maybe_trim__getdelimToo many open files in systemRead-only file system__mpn_divremCPU to programDevice not a stream_dl_strtoul__wcschrnul__strchrnul__mpn_mulJulpfmlib_getlhw_smpl__libc_start_main_impl__libc_message_implAddress family not supported by protocol/dev/null__pthread_mutex_unlock_full__pthread_mutex_lock_full/dev/fullExchange fullNumber of cycles in which one or more valid micro-ops did not dispatch due to BSR fullNumber of cycles in which one or more valid micro-ops did not dispatch due to GPR fullNumber of cycles in which one or more valid micro-ops did not dispatch due to FPR fullNumber of cycles in which one or more valid micro-ops did not dispatch due to ISSQ fullNumber of cycles in which one or more valid micro-ops did not dispatch due to SRQ fullNumber of cycles in which one or more valid micro-ops did not dispatch due to LRQ fullNumber of cycles in which one or more valid micro-ops did not dispatch due to ROB fullOperation not possible due to RF-killLevel 2 data/unified cache allocations without refillLevel 2 data/unified cache allocation without refillLevel 1 data cache allocation without refillLevel 2 data cache write refillLevel 1 data cache write refillLevel 1 data TLB write refillLevel 1 instruction cache refillLevel 2 data cache refillLevel 1 data cache refillLevel 2 data cache read refillLevel 1 data cache read refillLevel 1 data TLB read refillNo any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refillLevel 1 instruction TLB refillLevel 1 data TLB refillAttributable instruction memory access that causes a TLB refillAttributable memory-read or attributable memory-write operation that causes a TLB refillL1 stage-2 TLB refillExceptions taken locally, secure monitor callException taken, secure monitor callExceptions taken, hypervisor callException taken, hypervisor callExceptions taken, supervisor callException taken, supervisor callInterrupted system call_IO_flush_allAprilExclusive operation speculative executed - Store exclusive failExclusive operations speculative executed - STREX or STX failExclusive operation speculative executed - STREX or STX failmonitor at hypervisor levelmonitor at user levelmonitor at kernel level__syscall_do_cancelexclrx_scclE33-strerror-invalplural_evalglibc: fatal__gettext_extract_pluralBus access, peripheral____strtoul_l_internal____strtol_l_internal____strtoull_l_internal____strtoll_l_internal____strtof_l_internal____strtod_l_internal____strtold_l_internal__gconv_transform_ascii_internal__vfscanf_internal__gconv_transform_ucs2reverse_internal__gconv_transform_ucs4le_internal__gconv_transform_utf8_internal__gconv_transform_ucs4_internal__gconv_transform_ucs2_internalprintf_positionalBus access, normalstatus == __codecvt_partial__mbsrtowcs_l__strcasecmp_l__strncasecmp_l+%c %a %lE13-twomaskE12-onemaskName not unique on networkMachine is not on the network_obstack_newchunkInvalid cross-device linkIllegal seekkeld@dkuug.dk___pthread_rwlock_wrlock___pthread_rwlock_unlock___pthread_rwlock_rdlock___pthread_mutex_lock__wasm32_syscall_sentinel_checkStore Instruction architecturally executed, condition checkLoad Instruction architecturally executed, condition checkget_nprocs_fallback__readonly_area_fallbackLevel 2 data cache write-backLevel 1 data cache write-backLevel 2 data cache WriteBackLevel 1 data cache WriteBackFrilli__gconv_transform_internal_ascii=INTERNAL->asciihhi__translated_number_width__gconv_get_pathLRQ ordering flush_IO_wdefault_finish_IO_default_finishmhA Load hit store retry, VA match, PA mismatch__tsearchbsearchMarchBranch speculatively executed, indirect branchInstruction architecturally executed, immediate branchBranch speculatively executed, immediate branchInstruction architecturally executed, branchAug_nl_find_msgArgument list too longFile name too longMessage too longcorrupted size vs. prev_size while consolidatingOperation speculatively executed, data-processing__hash_stringoutstring_converted_wide_stringtopdown-retiringretry_ringStructure needs cleaningprecise event samplingenable hardware samplingpfm_arm_get_encodingpfm_perf_get_encodingpfm_arm_get_perf_encodingpfm_perf_get_perf_encodingarm_kunpengHisilicon Kunpengmg__malloc_hugepage_configrw_chgrnk_chg_dl_debug_vdprintf__printf_buffer_flush_dprintfperf__gconv_read_conf.confinf_IO_wfile_seekoff0123456789abcdef%p%t%g%t%m%t%fnumsize == densize__malloc_default_thp_pagesizenew_size > 0 && new_size < max_sizecorrupted size vs. prev_sizemap->l_tls_blocksize >= map->l_tls_initimage_size/sys/kernel/mm/transparent_hugepage/hpage_pmd_sizerealloc(): invalid next sizemalloc(): corrupted top sizeL2 TLB lookup miss using 512M page sizeL2 TLB lookup miss using 2M page sizeL2 TLB lookup miss using 64K page sizeL2 TLB lookup miss using 4K page sizerealloc(): invalid old sizefree(): invalid sizepfm_initializeExclusive operation speculatively executed - Store exclusiveExclusive operation speculatively executed - Load exclusiveSX Op non-issueLX Op non-issueFX Op non-issueBX Op non-issueIXB Op non-issueIXA Op non-issueCycle on which no operation issued because there were no operations to issueCycles in which no operation issued because there were no operations to issueTueinvalid event attributeObject is remote__wprintf_buffer_write__printf_buffer_write_IO_wdo_write_IO_new_file_writeLevel 2 data TLB refills on writeLevel 2 data TLB accesses on writeChecked data memory access, writeData memory access, writeBus access, writeLevel 2 data cache access, writeLevel 1 data cache access, writeUnaligned access, writeLevel 2 data/unified TLB access, writeLevel 1 data TLB access, writeLevel 2 data cache refill, writeLevel 1 data cache refill, writeLevel 2 data/unified TLB refill, writepfmlib_pmu_activate__lll_lock_wait_private__pthread_setcancelstateFile descriptor in bad state__gconv_transliterateClocks at the DMC clock ratepfm_terminatepfm_perf_terminateLevel 2 data cache invalidateLevel 1 data cache invalidateAddress already in use__gconv_transform_internal_ucs2reverse=INTERNAL->ucs2reverse__gettextparse_IO_new_proc_closeSVE predicated operations speculatively executed with a governing predicate in which at least one element is falseprecise__mpn_impn_mul_n_basecasefile->wide_stream._IO_write_base == file->next->write_basefile->stream._IO_write_base == file->next->write_baseInstruction architecturally executed (condition check pass) Write to translation table baseCPU architecturefailure__libc_cleanup_pop_restoreInstruction architecturally executed (condition check pass), unaligned load/storeOperation speculatively executed, load or storeLSMQ entry 15 was initiated by a storeOperation speculatively executed, storeInstruction architecturally executed (condition check pass) - Store*cp <= *repfmlib_get_pmu_by_type/sys/bus/event_source/devices/%s/typeWrong medium typeNo message of desired typeValue too large for defined data typewr_hit_spiperd_hit_spipewr_spiperd_spipewr_hit_cpiperd_hit_cpipewr_cpiperd_cpipeBroken pipeJune/sys/devices/system/cpu/onlineScu hwpf requests into the pipelineScu hwpf ld requests into the pipelinenext_linearm_xgeneApplied Micro X-Gene_nl_explode_nameinsert_moduleadd_modulecannot allocate link map for dlopen'd wasm modulecannot allocate name for dlopen'd wasm moduleread_sysfs_fileread_conf_fileIs a named type fileNot a XENIX named type fileStale file handleBus cycleDecode starved for instruction cycleFSU clocking gated off cycleWait state cycleOp dispatch stalled cyclegen_tracepoint_tablepfm_arm_validate_tablepfm_perf_validate_tableE06b-perf-in-tableE07-ac57-in-tableState not recoverableResource temporarily unavailableCycle on which no operation issued due to back-end resources being unavailableCycleis in which no operation issued due to back-end resources being unavailableCycles in which no operation issued due to back-end resources being unavailableRequired key not availableProtocol not availableNo locks availableNo XENIX semaphores availableNo CSI structure availableNo buffer space availableNo data availableNetwork is unreachableBus access, normal, cacheable, shareable__gconv_transform_internal_ucs4le=INTERNAL->ucs4le__wprintf_function_invoke__printf_function_invokefree(): too many chunks detected in tcachepfmlib_perf_encode_hw_cache__gconv_lookup_cache__gconv_load_cache/usr/lib/gconv/gconv-modules.cacheL1 instruction cacheLast level cacheL1 data cacheNo any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cacheFile too largeNumerical result out of rangeChannel number out of rangeLink number out of rangeInvalid exchangeBad message__libc_freeNo anodeRequest packets sent from this nodeSnoop packets sent from this nodeInterrupt related packets sent from this nodeData packets sent from this nodeInstructions architecturally executed (condition check pass, write to TTBR). Counts writes to TTBR0_EL1/TTBR1_EL1 in aarch64 modepfmlib_raw_pmu_encodepfmlib_perf_event_encodeNumber of cycles during which micro-op skid-buffer is back-pressuring decodegconv_parse_codeInvalid request code__printf_buffer_flush_fphex_to_wide__printf_buffer_flush_fp_to_widerceKey was rejected by serviceInappropriate ioctl for deviceNo space left on deviceNo such deviceToo many references: cannot splicebreak adjusted to free malloc space__getcwd__nptl_deallocate_tsd_itoa_wordNumber of times SPE has a sample record taken when the previous sampled operation has not yet completed its recordflux_rdsampling periodE21-unknown-is-notfoundE31-strerror-notfoundevent not foundNo medium foundtopdown-fe-boundtopdown-be-bound__pthread_unwind__tfind*outptrp + 4 > outendNo operation sent for execution on a slot due to the frontendInstructions can receive, but not sendCommunication error on sendNo operation sent for execution on a slot due to the backendoffset >= oldendbuf->base.write_end == buf->fp->_IO_write_endfile->wide_stream._IO_write_end == file->next->write_endfile->stream._IO_write_end == file->next->write_endfile->wide_stream._IO_write_ptr <= file->next->write_endfile->stream._IO_write_ptr <= file->next->write_endbuf->write_ptr != buf->write_endbuf->write_ptr < buf->write_endflux_wcmdflux_rcmdact_cmdpre_cmdlld/proc/sys/kernel/perf_event_paranoid/proc/sys/kernel/perf_counter_paranoidback_invalid%s/%s/idhhdLevel 2 not synchronizedIdentifier removedNo any micro operation is issued and meanwhile any load operation is not resolvedA Load hit store retry, VA match, store data not issuedCounts the number of micro-ops architecturally executedInstructions architecturally executedInstruction architecturally executedHalf precision floating-point operations sepculatively executedSingle precision floating-point operations sepculatively executedDouble precision floating-point operations sepculatively executedNon-scalable floating-point element operations sepculatively executedScalable floating-point element operations sepculatively executedSVE operations sepculatively executedAdvanced SIMD operations sepculatively executedISB barriers speculatively executedDSB barriers speculatively executedDMB barriers speculatively executedFloating-point instructions speculatively executedInteger data processing instructions speculatively executedLoad or store instructions speculatively executedStore instructions speculatively executedLoad instructions speculatively executedCryptographic instructions speculatively executedAdvanced SIMD instructions speculatively executedInstructions speculatively executedNon-scalable floating-point element operations speculatively executedScalable floating-point element operations speculatively executedSVE predicated operations speculatively executedSVE first-fault load operations speculatively executedSVE predicated operations with partially active predicates speculatively executedSVE predicated operations with no active predicates speculatively executedSVE predicated operations with all active predicates speculatively executedIndirect branches speculatively executedReturn branches speculatively executedImmediate branches speculatively executedPredictable branches speculatively executedMispredicted or not predicted branches speculatively executedISB barrier speculatively executedDSB barrier speculatively executedDMB barrier speculatively executedInteger data processing instruction speculatively executedSTREX pass exclusive instruction speculatively executedSTREX fail exclusive instruction speculatively executedLDREX exclusive instruction speculatively executedLoad or store instruction speculatively executedStore instruction speculatively executedLoad instruction speculatively executedVFP instruction speculatively executedAdvanced SIMD instruction speculatively executedSoftware of the PC instruction speculatively executedSoftware change of the PC instruction speculatively executedInstruction speculatively executedHalf-precision floating-point operation speculatively executedSingle-precision floating-point operation speculatively executedDouble-precision floating-point operation speculatively executedIndirect branch speculatively executedReturn branch speculatively executedImmediate branch speculatively executedPredictable branch speculatively executedMispredicted or not predicted branch speculatively executedStore uops executedFused uops executedLoad uops executedUops executedOperation not permittedmemory exhaustedProtocol family not supportedOperation not supportedProtocol not supportedSocket type not supportedInterrupted system call should be restarted.lib section in a.out corruptedmalloc(): smallbin double linked list corruptedmalloc(): unsorted double linked list corruptedfree(): chunks in smallbin corruptedMultihop attemptedInstruction architecturally executed, condition code check pass, write to TTBR This event only counts writes to TTBR0_EL1/TTBR1_EL1. Accesses to TTBR0_EL12/TTBR1_EL12 or TTBR0_EL2/TTBR1_EL2 are not countedFunction not implementedLevel 3 haltedLevel 2 haltedCounts all branches on the architecturally executed path that would incur cost if mispredictedIndirect branch instruction executed, but mis-predictedReturn branch instruction executed, but mis-predictedConditional branch instruction executed, but mis-predictedInstructions executed, mis-predicted branch. All instructions counted by BR_RETIRED that were not correctly predictedbuffer overflow detectedmalloc(): unaligned tcache chunk detectedTransport endpoint is already connectedTransport endpoint is not connectedNumber of cycles during which thread was available for dispatch but not selectedScu hwpf next line requests generatedE40-terminatedConnection refusedDestination address requiredBlock device requiredChange to Context ID retiredKey has expiredTimer expiredLink has been severedCounts number of time the Trace buffer current write pointer wrappedpinned_wordcopy_fwd_dest_aligned_wordcopy_fwd_alignedNumber of operations that might be sampled by SPE, whether or not the operation was sampledPackage not installedOperation canceledAttributable L2 TLB access This event counts on any access to the MMUTC (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabledAttributable L2 TLB accesses. Counts on any access to the MMUTC (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled/sys/kernel/mm/transparent_hugepage/enabledKey has been revokedE09-ac57-walkedAn external probe hit was retriedAn L2 evict operation was retriedPermission deniedOwner diedNumber of fused micro-ops dispatched__wasm32_syscall_reschedProtocol driver not attachedRemote address changedperf_event extendedResource deadlock avoidedDisk quota exceededNumber of times the SPE sample interval counter reaches zero and is reloadedWedLSMQ entry 0 was initiated by a loadOperation speculatively executed, loadInstruction architecturally executed (condition check pass) - LoadLevel 2 data TLB refills on readLevel 2 data TLB accesses on readL3 cache readChecked data memory access, readData memory access, readBus access, readLevel 2 data cache access, readLevel 1 data cache access, readUnaligned access, readLevel 2 data/unified TLB access, readLevel 1 data TLB access, readLevel 2 data cache refill, readLevel 1 data cache refill, readLevel 2 data/unified TLB refill, read%s%d:%s=%djmp_id=%x:%x val=%dnumsize == 1 && n < d__parse_one_specwc%s-rcE22-badattr-rcE20-unknown-rcE01-initialize-rc_int_malloc__libc_malloc glibc: malloc__libc_realloc__libc_callocException taken, smcE06-events-static__gconv_create_spectopdown-bad-specDec../stdio-common/printf_fphex.cgconv.cpfmlib_perf_event_pmu.cpfmlib_arm_perf_event.cpfmlib_perf_event.ccxa_atexit.crshift.cdl-find_object.c../sysdeps/unix/sysv/linux/getsysstats.cwstrops.cwfileops.cdl-tls.cwcsrtombs.cgrouping_iterator.ctpp.c../iconv/loop.cprintf_fp.c../iconv/skeleton.cpfmlib_common.cgconv_builtin.cgconv_dl.cvfprintf-internal.cvfscanf-internal.cmbsrtowcs_l.cstrtod_l.cpthread_mutex_lock.ctranslated_number_width.cXprintf_buffer_flush.ctsearch.cdl-printf.cgconv_conf.cXprintf_buffer_write.cgconv_simple.cwprintf_buffer_as_file.cprintf_buffer_to_file.ciofwide.c../sysdeps/unix/sysv/linux/getcwd.cmbrtowc.cmalloc.cwcrtomb.cgconv_db.carena.cXprintf_buffer_puts_1.cXprintf_buffer_pad_1.cXprintf_buffer_putc_1.c__correctly_grouped_prefixmb__parse_one_specmbFebwr_ddr_128brd_ddr_128bwr_ddr_64brd_ddr_64b_itowaadjust_wide_dataHit on prefetched data_itoa glibc: malloc arena_dl_readonly_area^[yY]inend != &bytebuf[MAX_NEEDED_INPUT]^[nN]IQ_IS_EMPTYISB_EMPTYROB_EMPTYROB_EMPTY_STQ_BUSYLD_COMP_WAIT_PFP_BUSYL1D_L2EV_RETRYL1D_EXPB_RETRYEA_MEMORYL2D_WB_CLEAN_COHERENCYL1D_WB_CLEAN_COHERENCY%a %b %e %H:%M:%S %Z %Y%a %b %e %H:%M:%S %YllXhhXExclusive operations speculatively executed - STREX or STXExclusive operation speculatively executed - STREX or STXPOSIXFujitsu A64FXLD_COMP_WAIT_PFP_BUSY_EXLD_COMP_WAIT_EXLD_COMP_WAIT_L2_MISS_EXLD_COMP_WAIT_L1_MISS_EXINST_SPEC_EXEC_STREXINST_SPEC_EXEC_LDREXExclusive operations speculatively executed - LDREX or LDXExclusive operation speculatively executed - LDREX or LDXlead_zero == 0 && int_no <= (uintmax_t) INTMAX_MAXcnt < MB_LEN_MAXniov < NIOVMAXCOUNTER_OVERFLOWL1_PIPE_COMP_GATHER_2FLOWL1_PIPE_COMP_SCATTER_1FLOWL1_PIPE_COMP_GATHER_1FLOWL1_PIPE_COMP_GATHER_0FLOWL1D_ST_RMWC/o Keld Simonsen, Skt. Jorgens Alle 8, DK-1615 Kobenhavn VPrefetch request from LSUPERF_COUNT_HW_CACHE_BPULIBPFM_FORCE_PMUperf_events raw PMUperf_events generic PMUBUS_WRITE_TOTAL_TOFUBUS_READ_TOTAL_TOFUAttributable L3 cache access This event counts for any cacheable read transaction returning data from the SCU, or for any cacheable write to the SCUAttributable L3 unified cache accesses. Counts any cacheable read transaction returning data from the SCU, or any cacheable write to the SCUCounts every beat of data transferred over the data channels between the core and the SCUL2D_TLBI_EXTnstatus == __GCONV_FULL_OUTPUTstatus == __GCONV_OK || status == __GCONV_EMPTY_INPUT || status == __GCONV_ILLEGAL_INPUT || status == __GCONV_INCOMPLETE_INPUT || status == __GCONV_FULL_OUTPUTLIBPFM_DEBUG_STDOUTINST_SPEC_EXEC_INTEGER_INSTEXCEPTION_TRAP_PABORTEXC_TRAP_PABORTEXCEPTION_PABORTEXC_PABORTEXCEPTION_TRAP_DABORTEXC_TRAP_DABORTEXCEPTION_DABORTEXC_DABORTCORRUPTSTALL_SLOTL2_MISS_COUNTL2D_TLBI_INTL1_PIPE1_COMP_PRD_CNTL1_PIPE0_COMP_PRD_CNTFLB_VAL_PRD_CNTFLA_VAL_PRD_CNTUOP_ONLY_COMMITSINGLE_MOVPRFX_COMMIT4INST_COMMIT3INST_COMMIT2INST_COMMIT1INST_COMMIT0INST_COMMITANSI_X3.4-1968//TRANSLIT,TRANSLITUOP_SPLITL1D_L2EV_HITL1D_LSMQ_HITL2D_HWPF_DMD_HITUNC_LLC_READ_HITL1D_EXPB_HITPAGE_WALK_L2_STAGE2_HITPAGE_WALK_L1_STAGE2_HITPAGE_WALK_L2_STAGE1_HITPAGE_WALK_L1_STAGE1_HITPAGE_WALK_L0_STAGE1_HITL1I_MISS_WAITL2_MISS_WAITL1_MISS_WAITEU_COMP_WAITBR_COMP_WAITFL_COMP_WAITLD_COMP_WAITOUTPUT_CHARSETBRANCH_SPEC_EXEC_RETUNC_LLC_EVICTBTB_MISPREDICTLDST_ALIGN_LATLD_ALIGN_LATLIBPFM_DISABLED_PMUSPERF_COUNT_SW_PAGE_FAULTSMINOR-FAULTSMAJOR-FAULTSPAGE-FAULTSL1D_L2EV_MISSL2D_HWPF_REQ_MISSL1D_CACHE_LATE_MISSLL_CACHE_MISSL2TLB_2M_PAGE_MISSL2TLB_512M_PAGE_MISSL2TLB_4K_PAGE_MISSL2TLB_64K_PAGE_MISSITB_MISSDTB_MISSL1D_EXPB_MISSLD_COMP_WAIT_L2_MISSLD_COMP_WAIT_L1_MISSL1I_CACHE_LMISSPERF_COUNT_HW_CACHE_LL:PREFETCH:MISSPERF_COUNT_HW_CACHE_L1I:PREFETCH:MISSPERF_COUNT_HW_CACHE_NODE:PREFETCH:MISSPERF_COUNT_HW_CACHE_L1D:PREFETCH:MISSPERF_COUNT_HW_CACHE_DTLB:PREFETCH:MISSPERF_COUNT_HW_CACHE_LL:WRITE:MISSPERF_COUNT_HW_CACHE_NODE:WRITE:MISSPERF_COUNT_HW_CACHE_L1D:WRITE:MISSPERF_COUNT_HW_CACHE_DTLB:WRITE:MISSPERF_COUNT_HW_CACHE_BPU:READ:MISSPERF_COUNT_HW_CACHE_LL:READ:MISSPERF_COUNT_HW_CACHE_L1I:READ:MISSPERF_COUNT_HW_CACHE_NODE:READ:MISSperf::PERF_COUNT_HW_CACHE_L1D:READ:MISSPERF_COUNT_HW_CACHE_ITLB:READ:MISSPERF_COUNT_HW_CACHE_DTLB:READ:MISSMEM_STALL_L2MISSMEM_STALL_L1MISSUNALIGNED_LDST_ACCESSBUS_ACCESSDATA_MEM_ACCESSBUS_NOT_NORMAL_ACCESSBUS_NORMAL_ACCESSBUS_PERIPH_ACCESSREMOTE_ACCESSBUS_WRITE_ACCESSDATA_MEM_WRITE_ACCESSUNALIGNED_WRITE_ACCESSL2D_WRITE_ACCESSL1D_WRITE_ACCESSL1I_CACHE_ACCESSL2D_CACHE_ACCESSL1D_CACHE_ACCESSUNALIGNED_ACCESSBUS_READ_ACCESSDATA_MEM_READ_ACCESSUNALIGNED_READ_ACCESSL2D_READ_ACCESSL1D_READ_ACCESSPERF_COUNT_HW_CACHE_LL:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_L1I:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_NODE:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_L1D:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_DTLB:PREFETCH:ACCESSPERF_COUNT_HW_CACHE_LL:WRITE:ACCESSPERF_COUNT_HW_CACHE_NODE:WRITE:ACCESSPERF_COUNT_HW_CACHE_L1D:WRITE:ACCESSPERF_COUNT_HW_CACHE_DTLB:WRITE:ACCESSPERF_COUNT_HW_CACHE_BPU:READ:ACCESSPERF_COUNT_HW_CACHE_LL:READ:ACCESSPERF_COUNT_HW_CACHE_L1I:READ:ACCESSPERF_COUNT_HW_CACHE_NODE:READ:ACCESSPERF_COUNT_HW_CACHE_L1D:READ:ACCESSPERF_COUNT_HW_CACHE_ITLB:READ:ACCESSPERF_COUNT_HW_CACHE_DTLB:READ:ACCESSINST_SPEC_EXEC_STREX_PASSUNC_DMC_DATA_TRANSFERSPERF_COUNT_HW_INSTRUCTIONSPERF_COUNT_HW_BRANCH_INSTRUCTIONSBRANCH-INSTRUCTIONSPERF_COUNT_SW_CPU_MIGRATIONSCPU-MIGRATIONSUNC_DMC_WRITESPERF_COUNT_HW_BRANCH_MISSESPERF_COUNT_HW_CACHE_MISSESL1-ICACHE-PREFETCH-MISSESL1-DCACHE-PREFETCH-MISSESNODE-PREFETCH-MISSESLLC-PREFETCH-MISSESDTLB-PREFETCH-MISSESBRANCH-MISSESL1-DCACHE-STORE-MISSESNODE-STORE-MISSESLLC-STORE-MISSESDTLB-STORE-MISSESCACHE-MISSESBRANCH-LOAD-MISSESL1-ICACHE-LOAD-MISSESL1-DCACHE-LOAD-MISSESNODE-LOAD-MISSESLLC-LOAD-MISSESITLB-LOAD-MISSESDTLB-LOAD-MISSESL1-DCACHE-STORESNODE-STORESLLC-STORESDTLB-STORESPERF_COUNT_HW_CPU_CYCLESPERF_COUNT_HW_REF_CPU_CYCLESarm_ac57::CPU_CYCLESBus cycles. This event duplicates CPU_CYCLESCNT_CYCLESWAIT_CYCLESPERF_COUNT_HW_BUS_CYCLESUNC_DMC_CYCLESCPU-CYCLESBUS-CYCLESREF-CYCLESPERF_COUNT_SW_CONTEXT_SWITCHESPERF_COUNT_SW_CGROUP_SWITCHESCONTEXT-SWITCHESCGROUP-SWITCHESL1-ICACHE-PREFETCHESL1-DCACHE-PREFETCHESNODE-PREFETCHESLLC-PREFETCHESDTLB-PREFETCHESBRANCHESPERF_COUNT_HW_CACHE_REFERENCESCACHE-REFERENCESBRANCH-LOADSL1-ICACHE-LOADSL1-DCACHE-LOADSNODE-LOADSLLC-LOADSITLB-LOADSDTLB-LOADSUNC_DMC_READSCS%H:%M:%SBUS_ACCESS_WRMEM_ACCESS_WRL2D_CACHE_REFILL_WRL1D_CACHE_REFILL_WRL2D_TLB_REFILL_WRL1D_TLB_REFILL_WRL2D_CACHE_WRL1D_CACHE_WRL2D_TLB_WRL1D_TLB_WRLOCAL_MEMORY_ERRORL1D_CACHE_REFILL_OUTERL1D_CACHE_REFILL_INNEREXCEPTION_TRAP_OTHEREXC_TRAP_OTHERL2HWPF_OTHERInstruction architecturally executed, Condition code check pass, write to CONTEXTIDRInstructions architecturally executed (condition check pass) - Write to CONTEXTIDRInstruction architecturally executed (condition check pass) - Write to CONTEXTIDRInstruction architecturally executed (condition check pass) Write to CONTEXTIDRSW_INCRInstruction architecturally executed, Condition code check pass, write to TTBREXCEPTION_TRAP_IRQEXC_TRAP_IRQEXCEPTION_IRQEXC_IRQExceptions taken locally, IRQEXCEPTION_TRAP_FIQEXC_TRAP_FIQEXCEPTION_FIQEXC_FIQExceptions taken locally, FIQUNC_CCPI_REQPRF_REQL2D_TLB_REQL2_TLB_REQL1D_LSMQ15_STREQL1D_LSMQ00_LDREQL1D_LHS_VANOTPSAMPLE_POPUNC_CCPI_SNOOPINST_SPEC_EXEC_NOPOperation speculatively executed - NOPL1I_PIPE_COMPL1_PIPE1_COMPL1_PIPE0_COMPLONGJMPINST_SPEC_EXEC_VFPWFIWFE_SLEEPTRB_WRAPL1D_LHS_OVRLAPISOEXCEPTION_RETURNEXC_RETURNSAMPLE_COLLISIONPERF_COUNT_SW_PAGE_FAULTS_MINCHAINEXCEPTION_TAKENEXC_TAKENNANL2D_CACHE_WB_CLEANL1D_CACHE_WB_CLEAN%a%N%f%N%d%N%b%N%s %h %e %r%N%C-%z %T%N%c%NL1D_L2EV_HITML1D_EXPB_HITMPML2D_CACHE_WB_VICTIML1D_CACHE_WB_VICTIML2D_WB_VICTIML1D_WB_VICTIMBUS_WRITE_TOTAL_MEMBUS_READ_TOTAL_MEMSTALL_BACKEND_MEML2D_SWAP_DML2D_CACHE_REFILL_DML1D_CACHE_REFILL_DMAMPERF_COUNT_HW_CACHE_LLoutbufstart == NULLresult == NULLstep->__end_fct == NULLfound->handle == NULLlistp != NULLelem != NULLl != NULLoutbuf != NULL && *outbuf != NULLirreversible != NULLcwd != NULLfunc != NULLL1D_LSMQ_FULLISB_FULLL1I_CACHE_PRF_REFILLL2D_WRITE_REFILLL1D_WRITE_REFILLL1D_TLB_WRITE_REFILLL2I_CACHE_REFILLL1I_CACHE_REFILLL3D_CACHE_REFILLL2D_CACHE_REFILLL1D_CACHE_REFILLL2D_READ_REFILLL1D_READ_REFILLL1D_TLB_READ_REFILLL2I_TLB_REFILLL1I_TLB_REFILLL2D_TLB_REFILLL1D_TLB_REFILLL1_STAGE2_TLB_REFILLarm_ac57::NO_SUCH_EVENT_AT_ALLL2_PIPE_COMP_ALLIF_IS_STALLINST_SPEC_EXEC_STREX_FAILL1D_BNKCFLPRX_VALL2D_HWPF_REQ_VALL1I_PIPE_VALL2_PIPE_VALEXB_VALFLB_VALEAGB_VALEXA_VALFLA_VALEAGA_VALL1_PIPE1_VALL1_PIPE0_VALL2D_CACHE_INVALL1D_CACHE_INVAL=ascii->INTERNAL=ucs2reverse->INTERNAL=ucs4le->INTERNAL=utf8->INTERNAL=ucs4->INTERNAL=ucs2->INTERNALBUS_ACCESS_NORMALL2D_CACHE_SWAP_LOCALSERROR_MASKIRQ_MASKFIQ_MASKRAW_UMASKL1_PIPE_ABORT_STLD_INTLKITLB_WALKDTLB_WALKPERF_COUNT_SW_CPU_CLOCKPERF_COUNT_SW_TASK_CLOCKCPU-CLOCKTASK-CLOCKPERF_COUNT_SW_PAGE_FAULTS_MAJBUS_WRITE_TOTAL_PCIBUS_READ_TOTAL_PCIPERF_COUNT_HW_CACHE_L1IGCONV_PATHL1D_PB_FLUSHBUS_ACCESS_PERIPHL1D_CACHE_PREFETCHL2_CACHE_PREFETCH STASH-MISMATCHBRANCH_SPEC_EXEC_IMM_BRANCHL2_PIPE_COMP_PF_L2MIB_MCHLIBPFM_DEBUGUNWINDINGHIT_ON_PRFL2D_CACHE_REFILL_PRFL1D_CACHE_REFILL_PRFL2D_CACHE_MIBMCH_PRFL1I_CACHE_PRFL2D_CACHE_REFILL_HWPRFL1D_CACHE_REFILL_HWPRFL2HWPF_STREAM_PFL1HWPF_STREAM_PFL2HWPF_INJ_ALLOC_PFL1HWPF_INJ_ALLOC_PFL2HWPF_INJ_NOALLOC_PFL1HWPF_INJ_NOALLOC_PFLD_COMP_WAIT_PFP_BUSY_SWPFINFFSU_CLOCK_OFFEXCEPTION_UNDEFEXC_UNDEFnumsize < RETURN_LIMB_SIZEwidth < IFMTSIZE*nsize < MPNSIZELIBPFM_ENCODE_INACTIVESX_NO_ISSUELX_NO_ISSUEFX_NO_ISSUEBX_NO_ISSUEIXB_NO_ISSUEIXA_NO_ISSUEperf::PERF_COUNT_HW_CACHE_L1D:WRITESAMPLE_FILTRATEL2D_INVALIDATEL1D_INVALIDATEL3D_CACHE_ALLOCATEL2D_CACHE_ALLOCATEL1D_CACHE_ALLOCATELIBPFM_VERBOSESVE predicated operations speculatively executed with a Governing predicate in which at least one element is FALSEINST_SPEC_EXEC_LOAD_STOREINST_SPEC_EXEC_STORE/IGNORE,IGNOREEA_COREL2D_HWPF_NEXT_LINEBUS_MASTER_CYCLEEXE_STALL_CYCLEWFE_WFI_CYCLEBSR_RECYCLEGPR_RECYCLEFPR_RECYCLEISSQ_RECYCLESRQ_RECYCLELRQ_RECYCLEROB_RECYCLEFETCH_BUBBLELL_CACHEL2I_CACHEL1I_CACHEL3D_CACHEL2D_CACHEL1D_CACHELANGUAGEL1_PIPE1_VAL_IU_TAG_ADRS_PFEL1_PIPE0_VAL_IU_TAG_ADRS_PFEPERF_COUNT_HW_CACHE_NODEL1_PIPE1_VAL_IU_TAG_ADRS_SCEL1_PIPE0_VAL_IU_TAG_ADRS_SCEL1D_LHS_FWDL1D_LHS_VANOSDLL_CACHE_MISS_RDL3D_CACHE_LMISS_RDL2D_CACHE_LMISS_RDL1D_CACHE_LMISS_RDBUS_ACCESS_RDMEM_ACCESS_RDREMOTE_ACCESS_RDL2D_CACHE_REFILL_RDL1D_CACHE_REFILL_RDL2D_TLB_REFILL_RDL1D_TLB_REFILL_RDLL_CACHE_RDL2D_CACHE_RDL1D_CACHE_RDL3_CACHE_RDL2D_TLB_RDL1D_TLB_RDBRANCH_SPEC_EXEC_INDSTALL_SLOT_FRONTENDPERF_COUNT_HW_STALLED_CYCLES_FRONTENDSTALL_FRONTENDIDLE-CYCLES-FRONTENDSTALLED-CYCLES-FRONTENDSTALL_SLOT_BACKENDPERF_COUNT_HW_STALLED_CYCLES_BACKENDSTALL_BACKENDIDLE-CYCLES-BACKENDSTALLED-CYCLES-BACKENDINST_SPEC_EXEC_SIMDL2D_HWPF_REQ_LDL1D_LSMQ15_STVLDL1D_LSMQ00_LDVLDSTALL_NOTSELECTEDUOPSFUSEDBR_MIS_PREDBR_PREDBRANCH_PREDBRANCH_MISPREDSVE_INST_RETIREDSIMD_INST_RETIREDUNALIGNED_LDST_RETIREDBR_RETIREDST_OP_RETIREDLD_OP_RETIREDFUSED_OP_RETIREDBR_RETURN_RETIREDTTBR_WRITE_RETIREDCID_WRITE_RETIREDPC_WRITE_RETIREDLD_RETIREDBR_MIS_PRED_RETIREDBR_RETURN_MIS_PRED_RETIREDBR_COND_MIS_PRED_RETIREDBR_IND_MIS_PRED_RETIREDBR_IMMED_RETIREDBUS_ACCESS_NOT_SHAREDBUS_ACCESS_SHAREDPARKEDMEM_ACCESS_CHECKEDMEM_ACCESS_WR_CHECKEDMEM_ACCESS_RD_CHECKEDSAMPLE_FEEDINST_SPEC_EXEC_LOADMEM_STALL_ANYLOADUNC_LLC_READPERF_COUNT_HW_CACHE_L1DEXCEPTION_SVCEXC_SVCEXCEPTION_HVCEXC_HVCINST_SPEC_EXEC_SOFT_PCEXCEPTION_SMCEXC_SMCMarvell ThunderX2 Node1 DMCMarvell ThunderX2 Node0 DMCEvict requests to LLCWriteback requests to LLCRead requests to LLCMarvell ThunderX2 node 1 LLCMarvell ThunderX2 node 0 LLCUNC_CCPI_GICINST_SPEC_EXECSVE_PRED_EMPTY_SPECSVE_MOVPRFX_SPECSTREX_SPECLDREX_SPECPOST_INDEX_SPECPRE_INDEX_SPECFP_MV_SPECSVE_MOVPRFX_U_SPECFP_CVT_SPECFP_ST_SPECASE_SVE_ST_SPECUNALIGNED_ST_SPECRC_ST_SPECSVE_INST_SPECEFFECTIVE_INST_SPECASE_INST_SPECUNALIGNED_LDST_SPECASE_SVE_INT_SPECSVE_LDFF_FAULT_SPECBR_RET_SPECBR_INDIRECT_SPECSTREX_PASS_SPECFP_SP_SCALE_OPS_SPECFP_HP_SCALE_OPS_SPECFP_SCALE_OPS_SPECFP_DP_SCALE_OPS_SPECFP_SP_FIXED_OPS_SPECFP_HP_FIXED_OPS_SPECFP_FIXED_OPS_SPECFP_DP_FIXED_OPS_SPECSVE_ST_SCATTER_SPECSVE_PRF_GATHER_SPECSVE_LD_GATHER_SPECFP_SP_SPECUOP_SPECFP_HP_SPECVFP_SPECFP_DP_SPECCRYPTO_SPECBR_RETURN_SPECSVE_PRED_NOT_FULL_SPECSVE_PRED_FULL_SPECSTREX_FAIL_SPECIEL_SPECSVE_PRED_PARTIAL_SPECASE_SVE_ST_MULTI_SPECASE_SVE_LD_MULTI_SPECSVE_MATH_SPECSVE_PRF_CONTIG_SPECBASE_ST_REG_SPECSVE_STR_REG_SPECSVE_LDR_REG_SPECBASE_LD_REG_SPECSVE_STR_PREG_SPECSVE_LDR_PREG_SPECIREG_SPECPRF_SPECSVE_LDFF_SPECPC_WRITE_SPECASE_SPECFP_RECPE_SPECPRD_SPECFP_LD_SPECASE_SVE_LD_SPECUNALIGNED_LD_SPECRC_LD_SPECBC_LD_SPECSVE_PRED_SPECBR_IMMED_SPECISB_SPECDSB_SPECDMB_SPECDCZVA_SPECFP_FMA_SPECASE_SVE_INT8_SPECASE_SVE_INT16_SPECASE_SVE_INT64_SPECASE_SVE_INT32_SPECL2D_CACHE_WBL1D_CACHE_WBUNC_LLC_WBBARRIER_SPEC_EXEC_ISBBarrier speculatively executed, ISBBARRIER_SPEC_EXEC_DSBbarrier speculatively executed, DSB0 <= p.exponent && p.exponent < 3 && p.exponent + to_shift < BITS_PER_MP_LIMBBARRIER_SPEC_EXEC_DMBBarrier speculatively executed, DMBL2I_TLBL1I_TLBL2D_TLBL1D_TLBPERF_COUNT_HW_CACHE_ITLBPERF_COUNT_HW_CACHE_DTLBUNC_CCPI_DATA??charset=nplurals=,ccs=plural=Hugepagesize:::hisi_sccl1_l3c9Hisilicon Kunpeng SCCL1 L3C9hisi_sccl5_l3c29Hisilicon Kunpeng SCCL5 L3C29hisi_sccl7_l3c19Hisilicon Kunpeng SCCL7 L3C19__gconv_transform_internal_utf8=INTERNAL->utf8hisi_sccl1_l3c8Hisilicon Kunpeng SCCL1 L3C8hisi_sccl5_l3c28Hisilicon Kunpeng SCCL5 L3C28hisi_sccl7_l3c18Hisilicon Kunpeng SCCL7 L3C18hisi_sccl3_l3c7hisi_sccl5_hha7CTI_TRIGOUT7Hisilicon Kunpeng SCCL3 L3C7Hisilicon Kunpeng SCCL5 HHA7arm_ac57ARM Cortex A57group_number.3257hisi_sccl5_l3c27Hisilicon Kunpeng SCCL5 L3C27hisi_sccl7_l3c17Hisilicon Kunpeng SCCL7 L3C17str_to_mpn.3407Cross-trigger Interface output trigger 7hisi_sccl3_l3c6hisi_sccl5_hha6CTI_TRIGOUT6Hisilicon Kunpeng SCCL3 L3C6Hisilicon Kunpeng SCCL5 HHA6hisi_sccl5_l3c26Hisilicon Kunpeng SCCL5 L3C26hisi_sccl7_l3c16Hisilicon Kunpeng SCCL7 L3C16Cross-trigger interface output trigger 6Cross-trigger Interface output trigger 6hisi_sccl3_l3c5hisi_sccl7_hha5CTI_TRIGOUT5Hisilicon Kunpeng SCCL3 L3C5Hisilicon Kunpeng SCCL7 HHA5hisi_sccl5_l3c25Hisilicon Kunpeng SCCL5 L3C25hisi_sccl1_l3c15Hisilicon Kunpeng SCCL1 L3C15A store was allocated LSMQ entry 15Cross-trigger interface output trigger 5Cross-trigger Interface output trigger 5__gconv_transform_internal_ucs4=INTERNAL->ucs4hisi_sccl3_l3c4hisi_sccl7_hha4CTI_TRIGOUT4Hisilicon Kunpeng SCCL3 L3C4Hisilicon Kunpeng SCCL7 HHA4printf_positional.3264hisi_sccl5_l3c24Hisilicon Kunpeng SCCL5 L3C24hisi_sccl1_l3c14Hisilicon Kunpeng SCCL1 L3C14Cross-trigger interface output trigger 4Cross-trigger Interface output trigger 4Cycles of that the number of issuing micro operations are less than 4pid >= 0 && sizeof (pid_t) <= 4lead_zero == 0 && int_no <= (uintmax_t) INTMAX_MAX / 4hisi_sccl7_ddrc3hisi_sccl5_ddrc3hisi_sccl3_ddrc3hisi_sccl1_ddrc3hisi_sccl3_l3c3hisi_sccl1_hha3TRCEXTOUT3BUS_WRITE_TOTAL_CMG3BUS_READ_TOTAL_CMG3Hisilicon Kunpeng SCCL7 DDRC3Hisilicon Kunpeng SCCL5 DDRC3Hisilicon Kunpeng SCCL3 DDRC3Hisilicon Kunpeng SCCL1 DDRC3Hisilicon Kunpeng SCCL3 L3C3Hisilicon Kunpeng SCCL1 HHA3outstring_converted_wide_string.3263arm_ac53ARM Cortex A53+45 3325-6543+45 3122-6543hisi_sccl7_l3c23Hisilicon Kunpeng SCCL7 L3C23hisi_sccl1_l3c13Hisilicon Kunpeng SCCL1 L3C13PE Trace unit extern output 3arm_thunderx2arm_v2arena_get2__gconv_transform_internal_ucs2=INTERNAL->ucs2add_alias2arm_n2hisi_sccl7_ddrc2hisi_sccl5_ddrc2hisi_sccl3_ddrc2hisi_sccl1_ddrc2hisi_sccl3_l3c2hisi_sccl1_hha2BUS_NORMAL_ACCESS_2Cavium ThunderX2Arm Neoverse V2TRCEXTOUT2Arm Neoverse N2EA_L2Attributable L3 cache allocation without refill This event counts any full cache line write into the L3 cache which does not cause a linefill, including Write-Backs from L2 to L3 and full-line writes which do not allocate into L2Attributable L3 data or unified cache allocations without a refill. Counts any full cache line write into the L3 cache which does not case a linefill, including write-backs from L2 to L3 and full line write which do not allocate into L2BUS_WRITE_TOTAL_CMG2BUS_READ_TOTAL_CMG2Hisilicon Kunpeng SCCL7 DDRC2Hisilicon Kunpeng SCCL5 DDRC2Hisilicon Kunpeng SCCL3 DDRC2Hisilicon Kunpeng SCCL1 DDRC2Hisilicon Kunpeng SCCL3 L3C2Hisilicon Kunpeng SCCL1 HHA2str_to_mpn.3442hisi_sccl7_l3c22Hisilicon Kunpeng SCCL7 L3C22hisi_sccl1_l3c12Hisilicon Kunpeng SCCL1 L3C12PE Trace unit extern output 2malloc(): corrupted unsorted chunks 2free(): unaligned chunk detected in tcache 2free(): double free detected in tcache 2arm_v1arm_n1tx2_ccpi1ch != 0xc0 && ch != 0xc1hisi_sccl7_ddrc1hisi_sccl5_ddrc1hisi_sccl3_ddrc1hisi_sccl1_ddrc1tx2_dmc1tx2_llc1hisi_sccl3_l3c1hisi_sccl3_hha1__printf_buffer_puts_1__printf_fp_buffer_1__mpn_addmul_1__mpn_submul_1__mpn_mul_1__wprintf_buffer_pad_1__printf_buffer_pad_1uncore_dmc_1uncore_l3c_1uncore_ccpi2_1Arm Neoverse V1TRCEXTOUT1ARM Neoverse N1An L2 evict operation hit in the L1An external probe hit in the L1An L2 evict operation hit a modified line in the L1An external probe hit a modified line in the L1A read modify write store was drained and updated the L1An L2 evict operation missed the L1An external probe missed the L1BUS_WRITE_TOTAL_CMG1BUS_READ_TOTAL_CMG1Hisilicon Kunpeng SCCL7 DDRC1Hisilicon Kunpeng SCCL5 DDRC1Hisilicon Kunpeng SCCL3 DDRC1Hisilicon Kunpeng SCCL1 DDRC1Hisilicon Kunpeng SCCL3 L3C1Hisilicon Kunpeng SCCL3 HHA1hisi_sccl5_l3c31Hisilicon Kunpeng SCCL5 L3C31hisi_sccl7_l3c21Hisilicon Kunpeng SCCL7 L3C21hisi_sccl1_l3c11Hisilicon Kunpeng SCCL1 L3C110.0001PE Trace unit extern output 1Cumulative duration of a PSTATE.I interrupt mask set to 1Cumulative duration of a PSTATE.F interrupt mask set to 1Cumulative duration of PSTATE.A interrupt mask set to 1empty == 1p.expsign == 0 || intdig_max == 1fcts.towc_nsteps == 1fcts.tomb_nsteps == 1wcp >= wstartp + 1tx2_ccpi0%s-code0hisi_sccl7_ddrc0hisi_sccl5_ddrc0hisi_sccl3_ddrc0hisi_sccl1_ddrc0tx2_dmc0tx2_llc0hisi_sccl3_l3c0hisi_sccl3_hha0uncore_dmc_0uncore_l3c_0uncore_ccpi2_0TRCEXTOUT0BUS_WRITE_TOTAL_CMG0BUS_READ_TOTAL_CMG0Hisilicon Kunpeng SCCL7 DDRC0Hisilicon Kunpeng SCCL5 DDRC0Hisilicon Kunpeng SCCL3 DDRC0Hisilicon Kunpeng SCCL1 DDRC0L1_PIPE1_VAL_IU_NOT_SEC0L1_PIPE0_VAL_IU_NOT_SEC0Hisilicon Kunpeng SCCL3 L3C0Hisilicon Kunpeng SCCL3 HHA0two_way_long_needle.3540hisi_sccl5_l3c30Hisilicon Kunpeng SCCL5 L3C30hisi_sccl7_l3c20Hisilicon Kunpeng SCCL7 L3C201997-12-20cy == 0 || p.tmp[p.tmpsize - 1] < 20hisi_sccl1_l3c10Hisilicon Kunpeng SCCL1 L3C10p.frac[p.fracsize - 1] < 10r00001.0A load has allocated LSMQ entry 0PE Trace unit extern output 0SVE first-fault load operations speculatively executed which set FFR bit to 0digcnt > 0result > 0need_frac_digits > 0replaced_arena->attached_threads > 0obj->counter > 0decimal_len > 0it->remaining > 0correction >= 0int_no > 0 && exponent == 0result->attached_threads == 0p->attached_threads == 0mutex->__data.__owner == 0info->extra == 0robust || (oldval & FUTEX_OWNER_DIED) == 0((uintptr_t) q & (uintptr_t) 0x1) == 0((unsigned long) ((char *) p + new_size) & (heap->pagesize - 1)) == 0cy != 0usize != 0 && cnt != 0bit != 0bits != 0errno != ERANGE || buf != NULL || size != 0(mode_flags & PRINTF_FORTIFY) != 0ISO-10646/UTF8/ISO-10646/UCS4/ISO-10646/UCS2/UNICODEBIG//UCS-4LE//ANSI_X3.4-1968//This event counts every cycle that no instructions are committed because the CSE is empty.This event counts every cycle that no instructions are committed, but counts at the time when commits MOVPRFX only.This event counts only Instruction Abort exceptions that are taken locally.This event counts only Data Abort or SError interrupt exceptions that are taken locally.This event counts only other synchronous exceptions that are taken locally.This event counts only Supervisor Call exceptions that are taken locally.Exception taken, Instruction Abort not Taken locally.Exception taken, other traps not Taken locally.Exception taken, Data Abort or SError not Taken locally.Exception taken, IRQ not Taken locally.Exception taken, FIQ not Taken locally.Level 2 data cache Write-Back, cleaning and coherency.Level 1 data cache Write-Back, cleaning and coherency.This event counts every cycle that no instructions are committed due to the lack of an available prefetch port.Exception taken, Instruction Abort.Level 1 instruction cache prefetch access count.Operation speculatively executed, floating-point.This event counts architecturally executed procedure return operations that defined by the BR_RETURN_RETIRED event.This event counts architecturally executed memory-reading instructions, as defined by the LD_RETIRED event.This event counts only software changes of the PC that defined by the instruction architecturally executed, condition code check pass and software change of the PC event.Count of the number of successful spill operations that the HHA has sent.Count of the number of spill operations that the HHA has sent.This event counts every cycle that the WFE/WFI instruction brings the instruction unit to a halt.This event counts the occurrence count of the micro-operation split.The number of all operations received by the HHA from another SCCL in this socket.The number of all operations received by the HHA from another socket.Exception taken, other synchronous.This event counts architecturally executed memory-reading instructions and memory-writing instructions, as defined by the LD_RETIRED and ST_RETIRED events.This event counts architecturally executed SIMD data-processing and load/store operations due to SVE instructions with a Governing predicate operand that determines the Active elements.Total write hits.Total read hits.Last Level cache miss.This event counts every cycle that no instructions are committed because the oldest and uncommitted integer load instruction waits for memory access.This event counts every cycle that no operation was committed because the oldest and uncommitted load/store operation waits for memory access.This event counts every cycle that no instructions are committed because the oldest and uncommitted integer load instruction waits for L1D, L2 and memory access.This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store operation waits for L1D, L2 and memory access.Data memory access.Attributable Bus access.Attributable Level 2 instruction cache access.Attributable Level 1 instruction cache access.Last Level cache access.Level 2 data cache access.Level 1 data cache access.This event counts every cycle that no instructions are committed because the oldest and uncommitted integer load instruction waits for L2 cache access.This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store operation waits for L2 cache access.This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.This event counts L2D_CACHE_REFILL caused by demand access.This event counts L1D_CACHE_REFILL caused by demand access.Unaligned access.Attributable Level 2 instruction TLB access.Attributable Level 1 instruction TLB access.Attributable Level 2 data or unified TLB access.Attributable Level 1 data or unified TLB access.Exclusive operation speculatively executed, Store-Exclusive pass.This event counts architecturally executed NOSIMD store operations that using SIMD and FP registers.This event counts architecturally executed NOSIMD load operations that using SIMD and FP registers.This event counts only IRQ exceptions that are taken locally, including Virtual IRQ exceptions.This event counts only FIQ exceptions that are taken locally, including Virtual FIQ exceptions.This event counts the number of flows of the scatter instructions.This event counts architecturally executed Instruction Synchronization Barrier instructions.This event counts architecturally executed Data Synchronization Barrier instructions.This event counts architecturally executed operations that prefetch memory due to SVE noncontiguous gather-prefetch instructions.This event counts architecturally executed indirect branch instructions that includes software change of the PC other than exception-generating instructions and immediate branch instructions.This event counts architecturally executed immediate branch instructions.This event counts architecturally executed floating-point data-processing instructions.This event counts architecturally executed integer data-processing instructions.This event counts architecturally executed Advanced SIMD data-processing instructions.This event counts architecturally executed store-exclusive instructions.This event counts architecturally executed load-exclusive instructions.This event counts architecturally executed operations that write to memory due to SVE noncontiguous scatter-store instructions.This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD multiple vector contiguous structure store instructions.This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD store instructions.This event counts architecturally executed operations that read from memory due to SVE noncontiguous gather-load instructions.This event counts architecturally executed memory read operations due to SVE First-fault and Non-fault load instructions.This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD multiple vector contiguous structure load instructions.This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD load instructions.This event counts architecturally executed prefetch operations due to scalar PRFM and SVE PRF instructions.This event counts architecturally executed SVE instructions.This event counts architecturally executed floating-point reciprocal estimate operations due to the Advanced SIMD scalar, Advanced SIMD vector, and SVE FRECPE and FRSQRTE instructions.This event counts architecturally executed math function operations due to the SVE FTSMUL, FTMAD, FTSSEL, and FEXPA instructions.This event counts all architecturally executed micro-operations.This event counts every cycle counted by the CPU_CYCLES event on that no operations are issued because the backend is unable to accept any operations.This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operations.This event counts architecturally executed inter-element manipulation operations.This event counts architecturally executed inter-register manipulation operations.Count of the number of retry that L3C suppresses the ring operations.This event counts architecturally executed floating-point move operations.DDRC total write operations.Count of the number of L3C back invalid operations.This event counts architecturally executed SIMD broadcast floating-point load operations.DDRC total read operations.Count of the number of retry that L3C suppresses the CPU operations.The number of read operations sent by HHA to DDRC which size is 64bytes.The number of write operations sent by HHA to DDRC which size is 128 bytes.The number of read operations sent by HHA to DDRC which size is 128 bytes.The number of write operations sent by HHA to DDRC which size is 64 bytes.This event counts prefetch requests to L2 cache generated by the other causes.Total write accesses.Total read accesses.DDRC read and write changes.DDRC rank commands.DDRC active commands.DDRC write commands.l3c precharge commands.DDRC precharge commands.DDRC read commands.This event counts architecturally executed Data Memory Barrier instructions, excluding the implied barrier operations of load/store operations with release consistency semantics.Local memory error.Exception taken, Data Abort or SError.This event counts architecturally executed operations that using predicate register.This event counts architecturally executed operations that read from memory due to an instruction that loads a general-purpose register.This event counts on writes to the PMSWINC register.This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.Branch speculatively executed, procedure return.This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception.This event counts every cycle that no instructions are committed, and the oldest and uncommitted instruction is an integer or floating-point instruction.This event counts every cycle that no instructions are committed, and the oldest and uncommitted instruction is a floating-point instruction.This event counts each executed exception return instruction.This event counts architecturally executed operations that prefetch memory due to an SVE predicated single contiguous element prefetch instruction.This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.This event counts every cycle that no instructions are committed, and the oldest and uncommitted instruction is a branch instruction.This event counts architecturally executed operations due to MOVPRFX instructions that are not fused with the prefixed instruction.This event counts architecturally executed operations due to MOVPRFX instructions, whether or not they are fused with the prefixed instruction.This event counts every architecturally executed instruction.Operation speculatively executed, Cryptographic instruction.This event counts architecturally executed instructions, excluding the MOVPRFX instruction.This event counts architecturally executed operations that write to memory due to an SVE STR instruction.This event counts architecturally executed operations that read from memory due to an SVE LDR instruction.This event counts architecturally executed operations that write to memory due to an SVE STR (predicate) instruction.This event counts architecturally executed operations that read from memory due to an SVE LDR (predicate) instruction.This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.This event counts architecturally executed operations that write to memory due to an instruction that stores a general-purpose register, excluding the 'DC ZVA' instruction.This event counts architecturally executed memory-writing instructions, as defined by the ST_RETIRED event. This event counts DCZVA as a store operation.This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.Sample Population.This event counts each exception taken.Sample Taken.Attributable Level 2 data cache Write-Back, victim.Attributable Level 1 data cache Write-Back, victim.Access to another socket in a multi-socket system.This event counts every cycle that no instructions are committed because the CSE is empty and the all store ports are full.Attributable Level 2 instruction cache refill.Level 1 instruction cache refill.Level 2 data cache refill.Level 1 data cache refill.Attributable Level 2 instruction TLB refill.Attributable Level 1 instruction TLB refill.Attributable Level 2 data TLB refill.Attributable Level 1 data TLB refill.Exception taken, Secure Monitor Call.Exception taken, Hypervisor Call.Exception taken, Supervisor Call.Exclusive operation speculatively executed, Store-Exclusive fail.This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Floating-point instructions section of SVE Reference Manual.This event counts architecturally executed integer arithmetic operations due to Advanced SIMD and SVE data-processing instructions listed in Integer instructions section of SVE Reference Manual.This event counts architecturally executed Advanced SIMD instructions, including the instructions listed in Non-SIMD SVE instructions section of SVE Reference Manual.This event counts architecturally executed SIMD instructions, excluding the Advanced SIMD scalar instructions and the instructions listed in Non-SIMD SVE instructions section of SVE Reference Manual.This event counts architecturally executed floating-point convert operations due to the scalar, Advanced SIMD, and SVE floating-point conversion instructions listed in Floating-point conversions section of SVE Reference Manual.Bus access, peripheral.Bus access, normal.Access to instruction TLB that causes a translation table walk.Access to data TLB causes a translation table walk.This event counts aborted requests in L1D pipelines that due to store-load interlock.Attributable Level 2 data cache write-back.Attributable Level 1 data cache write-back.This event counts L2D_CACHE_REFILL caused by hardware prefetch.This event counts L1D_CACHE_REFILL caused by hardware prefetch.This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.Branch speculatively executed, indirect branch.Branch speculatively executed, immediate branch.Instruction architecturally executed, mispredicted branch.This event counts every branch or other change in the program flow that the branch prediction resources are capable of predicting.This event counts each correction to the predicted program flow that occurs because of a misprediction from, or no prediction from, the branch prediction resources and that relates to instructions that the branch prediction resources are capable of predicting.Operation speculatively executed, integer data processing.Sample taken and not removed by filtering.Exclusive operation speculatively executed, Store-Exclusive.Exclusive operation speculatively executed, Load-Exclusive.Data memory access, write.Bus access, write.Attributable Level 2 data cache access, write.Attributable Level 1 data cache access, write.Unaligned access, write.Attributable Level 1 data or unified TLB access, write.Attributable Level 2 data cache refill, write.Attributable Level 1 data cache refill, write.Attributable Level 1 data TLB refill, write.Attributable Level 2 data cache invalidate.Attributable Level 1 data cache invalidate.Release consistency operation speculatively executed, Store-Release.Operation speculatively executed, load or store.Operation speculatively executed, store.This event counts energy consumption per cycle of core.Release consistency operation speculatively executed, Load-Acquire.Count of the number of write lines that come from this cluster of CPU core in spipe.Count of the number of read lines that come from this cluster of CPU core in spipe.This event counts completed requests in L1I cache pipeline.This event counts valid cycles of L1I cache pipeline.This event counts valid cycles of PRX pipeline.This event counts valid cycles of EXB pipeline.This event counts valid cycles of FLB pipeline.This event counts valid cycles of EAGB pipeline.This event counts valid cycles of EXA pipeline.This event counts valid cycles of FLA pipeline.This event counts valid cycles of EAGA pipeline.Sample collided with a previous sample.This event counts every cycle.Bus cycle.This event counts outstanding L1I cache miss requests per cycle.This event counts outstanding L1D cache miss requests per cycle.Cycle.Bus access, not Normal, Cacheable, Shareable.Bus access, Normal, Cacheable, Shareable.This event counts operations that cause a cache access to at least the L1I cache.This event counts operations that cause a refill of at least the L1I cache.This event counts operations that cause a cache access to at least the L1D cache.This event counts operations that cause a refill of at least the L1D cache.This event counts every write-back of data from the L1D cache.This event counts operations that cause a cache access to at least the L2 cache.This event counts operations that cause a refill of at least the L2 cache.This event counts every write-back of data from the L2 cache.This event counts architecturally executed operations that uses 'post-index' as its addressing mode.This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.No operation issued due to the frontend.This event counts every cycle counted by the CPU_CYCLES event on that no operations are issued because there are no operations available to issue for this PE from the frontend.No operation issued due to the backend.Operation speculatively executed.Predictable branch. Speculatively executed.Mispredicted or not predicted branch. Speculatively executed.This event counts every cycle that one instruction is committed.This event counts every cycle that only the MOVPRFX instruction is committed.This event counts every cycle that four instructions are committed.This event counts every cycle that two instructions are committed.This event counts every cycle that three instructions are committed.This event counts every cycle that only any micro-operations are committed.This event counts the number of times where 2 elements of the gather instructions became 2flows because 2 elements could not be combined.This event counts the number of times where 2 elements of the gather instructions became 1flow because 2 elements could be combined.Operation speculatively executed, load.Attributable Last level cache memory read.Last level cache miss, read.Data memory access, read.Bus access, read.Attributable Level 2 data cache access, read.Attributable Level 1 data cache access, read.Unaligned access, read.Attributable Level 1 data or unified TLB access, read.Access to another socket in a multi-socket system, read.Attributable Level 2 data cache refill, read.Attributable Level 1 data cache refill, read.Attributable Level 1 data TLB refill, read.Count of the number of operations that HHA has received from CCIX.This event counts every write to CONTEXTIDR.Exception taken, IRQ.Exception taken, FIQ.This event counts architecturally executed cryptographic instructions, except PMULL and VMULL.This event counts energy consumption per cycle of CMG local memory. It counts all events caused in measured CMG regardless of measured PE.This event counts write requests from measured CMG to measured CMG local memory. It counts all events caused in measured CMG regardless of measured PE.This event counts write requests from measured CMG to CMG3, if measured CMG is not CMG3. Otherwise, this event counts write requests from measured CMG to CMG3 local memory. It counts all events caused in measured CMG regardless of measured PE.This event counts write requests from measured CMG to CMG2, if measured CMG is not CMG2. Otherwise, this event counts write requests from measured CMG to CMG2 local memory. It counts all events caused in measured CMG regardless of measured PE.This event counts write requests from measured CMG to CMG1, if measured CMG is not CMG1. Otherwise, this event counts write requests from measured CMG to CMG1 local memory. It counts all events caused in measured CMG regardless of measured PE.This event counts write requests from measured CMG to CMG0, if measured CMG is not CMG0. Otherwise, this event counts write requests from measured CMG to CMG0 local memory. It counts all events caused in measured CMG regardless of measured PE.This event counts the number of times of L2 cache miss. It counts all events caused in measured CMG regardless of measured PE.This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access. It counts all events caused in measured CMG regardless of measured PE.This event counts write requests from measured CMG to tofu controller. It counts all events caused in measured CMG regardless of measured PE.This event counts write requests from measured CMG to PCI controller. It counts all events caused in measured CMG regardless of measured PE.This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch. It counts all events caused in measured CMG regardless of measured PE.This event counts completed requests in L2 cache pipeline. It counts all events caused in measured CMG regardless of measured PE.This event counts valid cycles of L2 cache pipeline. It counts all events caused in measured CMG regardless of measured PE.This event counts outstanding L2 cache miss requests per cycle. It counts all events caused in measured CMG regardless of measured PE.This event counts energy consumption per cycle of L2 cache. It counts all events caused in measured CMG regardless of measured PE.This event counts read requests from measured CMG local memory to measured CMG. It counts all events caused in measured CMG regardless of measured PE.This event counts read requests from CMG3 to measured CMG, if measured CMG is not CMG3. Otherwise, this event counts read requests from CMG3 local memory to measured CMG. It counts all events caused in measured CMG regardless of measured PE.This event counts read requests from CMG2 to measured CMG, if measured CMG is not CMG2. Otherwise, this event counts read requests from CMG2 local memory to measured CMG. It counts all events caused in measured CMG regardless of measured PE.This event counts read requests from CMG1 to measured CMG, if measured CMG is not CMG1. Otherwise, this event counts read requests from CMG1 local memory to measured CMG. It counts all events caused in measured CMG regardless of measured PE.This event counts read requests from CMG0 to measured CMG, if measured CMG is not CMG0. Otherwise, this event counts read requests from CMG0 local memory to measured CMG. It counts all events caused in measured CMG regardless of measured PE.This event counts read requests from tofu controller to measured CMG. It counts all events caused in measured CMG regardless of measured PE.This event counts read requests from PCI controller to measured CMG. It counts all events caused in measured CMG regardless of measured PE.Operation speculatively executed, Advanced SIMD.Operation speculatively executed, software change of the PC.This event counts architecturally executed SVE arithmetic operations. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC.This event counts architecturally executed SVE single-precision arithmetic operations. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC.This event counts architecturally executed SVE half-precision arithmetic operations. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC.This event counts architecturally executed SVE double-precision arithmetic operations. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC.This event counts architecturally executed v8SIMD and FP arithmetic operations. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.This event counts architecturally executed v8SIMD and FP half-precision arithmetic operations. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.This event counts architecturally executed v8SIMD and FP single-precision arithmetic operations. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.This event counts architecturally executed v8SIMD and FP double-precision arithmetic operations. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.Count of the number of prefetch drops from this L3C.Count of the number of write lines that hits in spipe of this L3C.Count of the number of read lines that hits in spipe of this L3C.Barrier speculatively executed, ISB.Barrier speculatively executed, DSB.Barrier speculatively executed, DMB.This event counts operations that cause a TLB access to at least the L2I TLB.This event counts operations that cause a TLB refill of at least the L2I TLB.This event counts operations that cause a TLB refill of at least the L1I TLB.This event counts operations that cause a TLB access to at least the L2D TLB.This event counts operations that cause a TLB refill of at least the L2D TLB.This event counts operations that cause a TLB refill of at least the L1D TLB.The number of all operations received by the HHA.:.This event counts for both Hypervisor Call exceptions taken locally in the hypervisor and those taken as an exception from Non-secure EL1.This event counts completed requests in L1D cache pipeline#1.This event counts valid cycles of L1D cache pipeline#1.This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1.This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1.This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.This event counts the number of 1 in the predicate bits of request in FLB pipeline, and corrects itself to be 16 when all bits are 1.This event counts the number of 1 in the predicate bits of request in FLA pipeline, and corrects itself to be 16 when all bits are 1.This event counts the number of 1 in the predicate bits of request in L1D cache pipeline#1, and corrects itself to be 16 when all bits are 1.This event counts the number of 1 in the predicate bits of request in L1D cache pipeline#0, and corrects itself to be 16 when all bits are 1.This event counts completed requests in L1D cache pipeline#0.This event counts valid cycles of L1D cache pipeline#0.This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0.This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0.This event counts the number of times where 2 elements of the gather instructions became 0flow because both predicate values are 0...hugepages-,perf_events raw event syntax: r[0-9a-fA-F]+sampling frequency (Hz)double free or corruption (!prev)double free or corruption (out)char *next_line(int, char *const, char **, char **, char *const)void _dl_debug_vdprintf(int, int, const char *, va_list)int __vfscanf_internal(FILE *, const char *, va_list, unsigned int)mp_limb_t __mpn_rshift(mp_ptr, mp_srcptr, mp_size_t, unsigned int)void printf_positional(struct __wprintf_buffer *, const wchar_t *, enum readonly_error_type, va_list, va_list *, int, const unsigned int *, wchar_t *, int, const char *, THOUSANDS_SEP_T, unsigned int)void printf_positional(struct __printf_buffer *, const char *, enum readonly_error_type, va_list, va_list *, int, const unsigned char *, char *, int, const char *, THOUSANDS_SEP_T, unsigned int)int __pthread_tpp_change_priority(int, int)int __gconv_transform_ascii_internal(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_ucs2reverse_internal(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_ucs4le_internal(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_utf8_internal(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_ucs4_internal(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_ucs2_internal(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_internal_ascii(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_internal_ucs2reverse(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_internal_ucs4le(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_internal_utf8(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_internal_ucs4(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int __gconv_transform_internal_ucs2(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, size_t *, int, int)int enlarge_userbuf(FILE *, off64_t, int)FILE *_IO_new_file_fopen(FILE *, const char *, const char *, int)int _IO_fwide(FILE *, int)void __wprintf_buffer_putc_1(struct __wprintf_buffer *, wchar_t)void *__tsearch(const void *, void **, __compar_fn_t)void *__libc_malloc2(size_t)void *__libc_calloc2(size_t)void __wprintf_buffer_pad_1(struct __wprintf_buffer *, wchar_t, size_t)void *_int_realloc(mstate, mchunkptr, size_t, size_t)void __printf_buffer_pad_1(struct __printf_buffer *, char, size_t)void _int_free_maybe_trim(mstate, size_t)void *_int_malloc(mstate, size_t)void __wprintf_buffer_write(struct __wprintf_buffer *, const wchar_t *, size_t)size_t __wcrtomb_internal(char *, wchar_t, mbstate_t *, size_t)char *__getcwd(char *, size_t)void __printf_buffer_write(struct __printf_buffer *, const char *, size_t)int heap_trim(heap_info *, size_t)void *__libc_realloc(void *, size_t)float ____strtof_l_internal(const char *, char **, int, locale_t)double ____strtod_l_internal(const char *, char **, int, locale_t)long double ____strtold_l_internal(const char *, char **, int, locale_t)size_t __mbsrtowcs_l(wchar_t *, const char **, size_t, mbstate_t *, locale_t)Unaligned accesses (includes speculatively executed SVE load and store operations that access at least one unaligned element address)void munmap_chunk(mchunkptr)topdown useful slots retiring uops (must be used in a group with the other topdown- events with slots as leader)topdown wasted slots due to bad speculation (must be used in a group with the other topdown- events with slots as leader)topdown wasted slots due to frontend (must be used in a group with the other topdown- events with slots as leader)topdown wasted slots due to backend (must be used in a group with the other topdown- events with slots as leader)void __printf_buffer_putc_1(struct __printf_buffer *, char)issue slots per logical CPU (used for topdown toplevel computation, must be first event in the group)double free or corruption (top)__mbsinit (data.__statep)!chunk_is_mmapped (oldp)chunk_is_mmapped (p)new_prio == -1 || (new_prio >= fifo_min_prio && new_prio <= fifo_max_prio)previous_prio == -1 || (previous_prio >= fifo_min_prio && previous_prio <= fifo_max_prio)Level 1 data cache write-backs (clean and coherency eviction)Level 1 data cache write-backs (victim eviction)listp->slotinfo[cnt].gen <= GL(dl_tls_generation)void *_dl_allocate_tls_init(void *, _Bool)corrupted double-linked list (not small)(nil)free(): invalid next size (normal)chunk_main_arena (bck->bk)malloc(): largebin double linked list corrupted (bk)raise ran during outward park propagation (machinery bug)malloc(): largebin double linked list corrupted (nextsize)((char *) p + new_size) == ((char *) heap + heap->size)(state->__count & 7) <= sizeof (state->__value)void remove_from_free_list(mstate)void detach_arena(mstate)void *sysmalloc(size_t, mstate)Release consistency instructions speculatively executed (store-release)Release consistency instruction speculatively executed (store-release)Release consistency instructions speculatively executed (load-acquire)Release consistency instruction speculatively executed (load-acquire)chunk_main_arena (fwd)longjmp while a C++ exception is unwinding (the phantom-exception hazard)throw while a longjmp is in transit (the converse phantom hazard)mstate get_free_list(void)void __gconv_get_path(void)malloc(): mismatching next->prev_size (unsorted)malloc(): invalid next size (unsorted)malloc(): invalid size (unsorted)malloc(): invalid next->prev_inuse (unsorted)Attributable L2 data or unified TLB refills. Counts on any refill of the L2TLB caused by either an instruction or data access (MMU must be enabled)Attributable L2 data or unified TLB accesses. Counts on any access to the L2 TLB caused by a refill of any of the L1 TLB (MMU must be enabled)(unsigned long) (newsize) >= (unsigned long) (nb)(unsigned long) (size) >= (unsigned long) (nb)cnt_after <= sizeof (data->__statep->__value.__wchb)inlen_after <= sizeof (state->__value.__wchb)cnt < sizeof (map) / sizeof (map[0])No OS (raw PMU)e != EDEADLK || (kind != PTHREAD_MUTEX_ERRORCHECK_NP && kind != PTHREAD_MUTEX_RECURSIVE_NP)(unsigned long) (old_size) < (unsigned long) (nb + MINSIZE)new_size > 0 && new_size < (long) (2 * MINSIZE)Data memory write accesses (includes SVE)Data memory read accesses (includes SVE)chunksize_nomask (p) == (0 | PREV_INUSE)inend - inptr > (state->__count & ~7)inptr - bytebuf > (state->__count & 7)int_no <= (uintmax_t) (exponent < 0 ? (INTMAX_MAX - bits + 1) / 4 : (INTMAX_MAX - exponent - bits + 1) / 4)dig_no > int_no && exponent <= 0 && exponent >= MIN_10_EXP - (DIG + 2)cy == 1 || (p.frac[p.fracsize - 2] == 0 && p.frac[0] == 0)(old_top == initial_top (av) && old_size == 0) || ((unsigned long) (old_size) >= MINSIZE && prev_inuse (old_top) && ((unsigned long) old_end & (pagesize - 1)) == 0)struct exit_function *__new_exitfn(struct exit_function_list **)int __internal_atexit(void (*)(void *), void *, void *, struct exit_function_list **)void __printf_fp_buffer_1(struct __printf_buffer *, locale_t, char, char, unsigned int, const struct printf_info *, const void *const *)void __printf_fphex_buffer(struct __printf_buffer *, const char *, const struct printf_info *, const void *const *)int _dl_find_object_slow(void *, struct dl_find_object *)int __pthread_mutex_lock_full(pthread_mutex_t *)int ___pthread_mutex_lock(pthread_mutex_t *)int ucs4le_internal_loop(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, const unsigned char *, size_t *)int __gconv(__gconv_t, const unsigned char **, const unsigned char *, unsigned char **, unsigned char *, size_t *)int ucs2reverse_internal_loop_single(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, unsigned char *, size_t *)int utf8_internal_loop_single(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, unsigned char *, size_t *)int ucs2_internal_loop_single(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, unsigned char *, size_t *)int internal_ascii_loop_single(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, unsigned char *, size_t *)int internal_ucs2reverse_loop_single(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, unsigned char *, size_t *)int internal_utf8_loop_single(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, unsigned char *, size_t *)int internal_ucs2_loop_single(struct __gconv_step *, struct __gconv_step_data *, const unsigned char **, const unsigned char *, unsigned char **, unsigned char *, size_t *)size_t __wcsrtombs(char *, const wchar_t **, size_t, mbstate_t *)size_t __mbrtowc(wchar_t *, const char *, size_t, mbstate_t *)_Bool __grouping_iterator_next(struct grouping_iterator *)_Bool __wprintf_buffer_flush(struct __wprintf_buffer *)_Bool __printf_buffer_flush(struct __printf_buffer *)struct __gconv_loaded_object *__gconv_find_shlib(const char *)const char *str_to_mpn(const char *, int, mp_limb_t *, mp_size_t *, intmax_t *, const char *, size_t, const char *)void __printf_buffer_puts_1(struct __printf_buffer *, const char *)int __translated_number_width(locale_t, const char *, const char *)void __gconv_release_step(struct __gconv_step *)void __gconv_get_builtin_trans(const char *, struct __gconv_step *)void __wprintf_buffer_as_file_commit(struct __wprintf_buffer_as_file *)void __printf_buffer_as_file_commit(struct __printf_buffer_as_file *)void __printf_buffer_flush_to_file(struct __printf_buffer_to_file *)void do_release_shlib(const void *, VISIT, void *)wint_t _IO_wfile_underflow(FILE *)!newp || chunk_is_mmapped (mem2chunk (newp)) || ar_ptr == arena_for_chunk (mem2chunk (newp))!victim || chunk_is_mmapped (mem2chunk (victim)) || ar_ptr == arena_for_chunk (mem2chunk (victim))!victim || chunk_is_mmapped (mem2chunk (victim)) || &main_arena == arena_for_chunk (mem2chunk (victim))!mem || chunk_is_mmapped (mem2chunk (mem)) || av == arena_for_chunk (mem2chunk (mem))lead_zero <= (base == 16 ? ((uintmax_t) exponent - (uintmax_t) INTMAX_MIN) / 4 : ((uintmax_t) exponent - (uintmax_t) INTMAX_MIN))int_no == 0 && *startp != L_('0')'0' <= *p && *p <= '9'wstartp[0] == '1'((wchar_t *) data.__outbuf)[-1] == L'\0'data.__outbuf[-1] == '\0'! "invalid format specifier"DYNAMIC LINKER BUG!!!Unknown error : hwjs-user-rt VIOLATION[lane %u]: lane_arena_reset of lane %u from an instance bound to lane %d — self-lane only hwjs-user-rt VIOLATION[lane %u]: fork child collapse to lane %u from an instance bound to lane %d — the child keeps the CALLER's lane (I1 keep-caller-index); self-lane only hwjs-user-rt VIOLATION[lane %u]: double frame_free of %px %s 0x%llx %s (%s.%d): guessing plm from %s PMU plm=0x%x pmu: %s events %s and %s have the same code 0x%x Fatal glibc error: gconv module reference counter overflow warning: mismatch attr struct size user=%d libpfm=%zu %s (%s.%d): pfmlib_check_struct: user size too small %zu %s (%s.%d): idpath=%s:%s id=%llu %s %llu hwjs-user-rt VIOLATION[lane %u]: fork child collapse to lane %u >= cap %u hwjs-user-rt VIOLATION[lane %u]: lane_assert_gen of lane %u >= cap %u hwjs-user-rt VIOLATION[lane %u]: lane detach of lane %u >= cap %u hwjs-user-rt VIOLATION[lane %u]: lane_arena_reset of UNOCCUPIED lane %u %s (%s.%d): no core CPU PMU, going with default hwjs-user-rt VIOLATION[lane %u]: take handle mismatch (slot handle %px owner-word=%px id-via-frame-header[h+4]=%px, expected handle %px) — balance take consumed a stranger's set hwjs-user-rt VIOLATION[lane %u]: adoption: take owner mismatch (slot handle %px owner-word=%px id-via-frame-header[h+4]=%px, expected owner-word %px) — a handle that crossed a native frame is being adopted by an unrelated bracket pmu: %s event%d: %s :: numasks (%d) invalid more events exists %s (%s.%d): pfmlib_check_struct: invalid extra bits hwjs-user-rt VIOLATION[lane %u]: lane generation mismatch on lane %u: driver carries gen %u, occupancy table holds gen %u — a STALE lane binding (the lane was detached and re-attached under this driver); refusing before any slot access %s (%s.%d): PMU %s does not support RAW umasks %s (%s.%d): too many attributes hwjs-user-rt VIOLATION[lane %u]: xfer verdict set-over-set: slot holds kind %u (next %px) at a new verdict kind %u (next %px) — the single-occupancy transfer slot was not consumed by the driver's __hwjs_xfer_take between resumes %s: %s: %s%s%s%s%s %s %s %s (%s.%d): too many events for %s %s (%s.%d): max encoding too high (%d > %d) for %s %s (%s.%d): trying %s %s (%s.%d): cannot find attribute %s %s (%s.%d): activated %s %s (%s.%d): %d %d %d %d %d %s %s (%s.%d): %d %d %d %s [UNC=0x%llx] %s [0x%x] %s PERF[type=%x config=0x%llx config1=0x%llx excl=%d excl_user=%d excl_kernel=%d excl_hv=%d excl_host=%d excl_guest=%d period=%llu freq=%d precise=%d pinned=%d] %s %s (%s.%d): default OS layer: %s Fatal glibc error: %s:%s (%s): assertion failed: %s PMU forced to %s (%s) : %s %s (%s.%d): raw umask (%s) is not a number hwjs-user-rt VIOLATION[lane %u]: DS region arena BIND failed for lane %u: SYS_mmap of %u bytes returned %d — true OOM at the --max-memory ceiling, not a soft cap hwjs-user-rt VIOLATION[lane %u]: frame arena OUT OF MEMORY: SYS_mmap of a new segment failed (live %u, allocs %u, high-water %u, request %u, segs %u) -- true OOM at the --max-memory ceiling, not a soft cap hwjs-user-rt VIOLATION[lane %u]: region_alloc non-power-of-two align %u (count %u stride %u policy %u) — the carve mask requires a power of two pmu: %s event%d: %s :: ngrp must be zero pmu: %s event%d: %s :: ngrp cannot be zero pmu: %s event%d: %s :: no description pmu: %s event%d:%s umask%d: %s :: no description %s (%s.%d): %d PMU blacklisted, skipping initialization hwjs-user-rt VIOLATION[lane %u]: orphan at clear: parked slot not empty at bracket entry (handle %px owner-word=%px id-via-frame-header[h+4]=%px) — a leaked slice reached the next bracketed call %s (%s.%d): cannot mix raw umask with umask hwjs-user-rt VIOLATION[lane %u]: set-over-set: parked slot not empty at a new park (orphaned handle %px owner-word=%px id-via-frame-header[h+4]=%px; incoming handle %px owner-word=%px) — a coroutinized frame parked under a NATIVE caller and the witness reached the next park hwjs-user-rt VIOLATION[lane %u]: park result taken with reason %u still pending — resumed without the pump servicing the park Fatal glibc error: Cannot allocate TLS block hwjs-user-rt VIOLATION[lane %u]: status_adopt_top on a LINKED frame %px (link=%u) — the adopted top must be the chain root (link 0 by frame_alloc construction); a linked top is a baton-protocol breach hwjs-user-rt VIOLATION[lane %u]: RT op on lane %u >= lane cap %u — a driver bound an out-of-range lane id (occupancy bitmap %x); the cap is the boot/manifest parameter, overflow at ATTACH is the catchable EAGAIN, but an op past the cap is a protocol breach hwjs-user-rt VIOLATION[lane %u]: lane_arena_reset of lane %u (0 is the process main; >= cap %u is out of range) — refusing hwjs-user-rt VIOLATION[lane %u]: lane detach of lane %u NOT at rest (inslice=%u parked=%px reason=%u lj=%u xfer=%u status=%s) — a detach mid-flight would orphan in-transit state silently; refusing hwjs-user-rt VIOLATION[lane %u]: lane_arena_reset of lane %u MID-FLIGHT (inslice=%u lj=%u xfer=%u) — not at a thread terminus; refusing hwjs-user-rt VIOLATION[lane %u]: status-channel clear of %s but the live status is %s (%s) — a consume raced or mis-targeted its raise; refusing hwjs-user-rt VIOLATION[lane %u]: longjmp on a jmp_buf that no setjmp initialized (activation id 0, value %d) — uninitialized or clobbered buffer; refusing rather than a silent wrong-frame landing hwjs-user-rt VIOLATION[lane %u]: lj_arm while a transfer is already in flight (pending owner_off %u) — nested cross-frame longjmp without a landing hwjs-user-rt VIOLATION[lane %u]: lj fate log overflow at free of handle-offset=%u (pending transfer owner_off=%u, %u frees logged) — the discard walk outran the witness; a saturated log would misreport a freed child as alive hwjs-user-rt VIOLATION[lane %u]: sj_record against a non-live frame handle %px — setjmp in a frame the arena does not carry live hwjs-user-rt VIOLATION[lane %u]: xfer_return on a non-live frame handle %px — completion of a frame the arena does not carry live hwjs-user-rt VIOLATION[lane %u]: xfer_descend on a non-live child frame handle %px — a drive_abi=3 transfer references a handle the arena does not carry live hwjs-user-rt VIOLATION[lane %u]: region_restore checkpoint %u ahead of the live sequence %u — a watermark from a future or foreign save pmu: %s event%d: %s :: invalid type hwjs-user-rt VIOLATION[lane %u]: lane detach of UNOCCUPIED lane %u (occupancy bitmap %x) — double detach or a never-attached lane hwjs-user-rt VIOLATION[lane %u]: lane detach of lane %u from an instance bound to lane %d — a Worker may detach only ITS OWN lane hwjs-user-rt VIOLATION[lane %u]: status_adopt_top baton %px is not a live arena frame pmu: %s event%d: %s umask%d :: no name hwjs-user-rt VIOLATION[lane %u]: status_baton child %px is not a live arena frame — the baton names a torn-down or foreign handle %s (%s.%d): cloning static event table %s (%s.%d): perf::%s not available hwjs-user-rt VIOLATION[lane %u]: noreturn child COMPLETED (handle %px owner %px%s) — contract breach, trapping at the caller's unreachable hwjs-user-rt VIOLATION[lane %u]: user park with a stale pending reason %u (new reason %u) — the pump failed to clear the previous service %s (%s.%d): %d PMU detected out of %d supported %s (%s.%d): OS layer %s activated *** %s ***: terminated hwjs-user-rt VIOLATION[lane %u]: longjmp to a dead or reused setjmp frame (pending owner_off %u gen %u) — §C6 generation mismatch; the recording frame was torn down or its slot reused hwjs-user-rt VIOLATION[lane %u]: lane detach of lane %u lost an occupancy race (pre-op bitmap %x carries no bit) — a concurrent detach of the SAME lane; single-writer-per-lane is breached hwjs-user-rt VIOLATION[lane %u]: fork child collapse to UNOCCUPIED lane %u (occupancy bitmap %x) — the copied occupancy table does not carry the calling lane; skewed fork payload %s (%s.%d): %s: unsupported count=%d %s (%s.%d): unsupported event type=%d %s (%s.%d): added default %s for group %d %s (%s.%d): no default found for event %s unit mask group %d hwjs-user-rt VIOLATION[lane %u]: DS region request too large (count %u * stride %u = %u bytes > arena %u) — single region exceeds the whole arena hwjs-user-rt VIOLATION[lane %u]: DS region free-list overflow returning [off=%u size=%u] (%u blocks live, arena high-water %u, %u live regions) — coalesce saturated; a dropped block would silently leak the arena hwjs-user-rt VIOLATION[lane %u]: DS region registry overflow (%u live, allocs %u) at region_alloc(count=%u stride=%u align=%u policy=%u) — raise HWJS_REGION_MAX cannot allocate memory for thread-local data: ABORT %s (%s.%d): %s PMU not exported by OS %s (%s.%d): PMU %s does not support PFM_OS_NONE LIBPFM4-PROBE-END hwjs-user-rt VIOLATION[lane %u]: status_adopt_top with live status %s (%s) — the terminus PARKED row ran without a live PARKED hwjs-user-rt VIOLATION[lane %u]: status_baton with live status %s (%s) — the dispatch PARKED arm ran without a live PARKED %s E00-setenv 0 Fatal glibc error: Internal __libc_message error. Too many arguments. hwjs-user-rt VIOLATION[lane %u]: status-channel raise of %s over live %s (live %s; incoming %s) — at most one non-NORMAL outcome may be in flight (I2); %s. Refusing. hwjs-user-rt VIOLATION[lane %u]: status-channel dispatch abort: %s (%s) arrived at a dispatch that cannot service it — at a cleanup-context (stash) site this is the two-in-flight collision: the frame holds a STASHED UNWINDING exception and a destructor/cleanup raised %s during its unwind (longjmp-across-destructors / throw-during-unwind made LOUD, I2/I4; at most one non-NORMAL outcome may be in flight). Refusing. hwjs-user-rt VIOLATION[lane %u]: in-wasm flat driver: unexpected xfer verdict kind %u (handle %px) — the per-resume verdict slot returned NONE/unknown where a transfer was required (a missing __hwjs_xfer_* emission or a double-take). Refusing. hwjs-user-rt VIOLATION[lane %u]: status-channel dispatch abort on status word %u (%s; live %s) — a corrupt channel word at a call-site dispatch, or a live PARKED at a resume edge (a frame is resumed only by a RETURN verdict; falling into the park arm would baton against a completed child). Refusing. The futex facility returned an unexpected error code. Failed loading %lu audit modules, %lu are supported. hwjs-user-rt VIOLATION[lane %u]: drive DONE_TOP with live status %u (%s; %s) — the chain root completed while a PARKED word survived completion (parks are consumed by the PARK leg; a live PARKED at DONE_TOP is a machinery bug). Refusing rather than reporting a clean DONE. *** procfs could not open *** *** %n in writable segments detected *** *** invalid %N$ use detected *** hwjs-user-rt VIOLATION[lane %u]: DS region arena exhausted (size %u, high-water %u, live %u, allocs %u; request count=%u stride=%u align=%u) — resize HWJS_REGION_ARENA_SIZE (a measurement, not a mystery) hwjs-user-rt VIOLATION[lane %u]: drive PARK leg with live status %u (%s) — a PARK verdict arrived while an UNWINDING/LONGJMP transit is in flight (machinery bug; parks are raised from NORMAL only) hwjs-user-rt VIOLATION[lane %u]: park raised over live %s (%s; self %px) — a park exit ran during an UNWINDING/LONGJMP transit (machinery bug: parks are raised from NORMAL only) %s (%s.%d): %d %d RAW_UMASK (0x%x) hwjs-user-rt VIOLATION[lane %u]: lane attach to OCCUPIED lane %u (occupancy bitmap %x, generation %u) — two Workers on one lane; the per-lane guards cannot see this collision, so the occupancy table refuses it here (the set-over-set two-driver detector's replacement) pmu: %s event%d: :: no name (prev event was %s) hwjs-user-rt VIOLATION[lane %u]: cross-lane status_adopt_top: baton %px carries lane tag %u, adopting lane is %u — a foreign lane's chain reached this lane's terminus (F86 named refusal; the I3-1 fork-child lane-skew armor) hwjs-user-rt VIOLATION[lane %u]: lane attach of lane %u from an instance bound to lane %d — a Worker may attach only ITS OWN lane (self-attach; the clone-side lane allocator is a later step) hwjs-user-rt VIOLATION[lane %u]: cross-lane xfer_return: frame %px carries lane tag %u, returning lane is %u — a foreign lane's frame completed on this lane's driver (F86 named refusal) hwjs-user-rt VIOLATION[lane %u]: cross-lane sj_record: frame %px carries lane tag %u, recording lane is %u — a foreign lane's frame reached this lane's setjmp (F86 named refusal) hwjs-user-rt VIOLATION[lane %u]: cross-lane xfer_descend: child %px carries lane tag %u, descending lane is %u — a foreign lane's frame entered this lane's drive chain (F86 named refusal) hwjs-user-rt VIOLATION[lane %u]: cross-lane status_baton: child %px carries lane tag %u, batoning lane is %u — a foreign lane's frame reached this lane's dispatch PARKED arm (F86 named refusal) hwjs-user-rt VIOLATION[lane %u]: cross-lane frame_free: pointer %px lies in lane %u's arena span, freed from lane %u — a foreign lane's frame reached this lane's teardown (single-writer-per-lane; F86 named refusal) hwjs-user-rt VIOLATION[lane %u]: cross-lane frame_free of %px: chunk lane tag %u != this lane %u — a foreign lane's live frame reached this lane's teardown (single-writer-per-lane; F86 named refusal) hwjs-user-rt VIOLATION[lane %u]: drive_adopt_parked with an empty v2 parked slot — a PARKED channel reached the terminus but no leaf was published (park_exit protocol breach) hwjs-user-rt VIOLATION[lane %u]: park exit under live PARKED whose baton %px is not self %px — the dispatch arm's baton and the suspending frame disagree (park protocol breach) hwjs-user-rt VIOLATION[lane %u]: drive PARK leg: channel baton %px is not the resumed frame %px — the last batoner/parker and the driver's resume target disagree (status-channel park protocol breach) hwjs-user-rt VIOLATION[lane %u]: status_baton found a null parked baton — PARKED committed without a payload (raise-ordering breach) hwjs-user-rt VIOLATION[lane %u]: longjmp target not found (jmp_id=%x:%x value=%d) — the activation id matched no live setjmp registration on the whole chain (dead, stale, or foreign jmp_buf; C11 7.13.2.1 UB made loud, never a silent wrong-frame landing) hwjs-user-rt VIOLATION[lane %u]: uncaught exception reached the drive terminus (exception header %px) — no frame between the raise and the outermost frame consumed UNWINDING (C-only weak fallback; libc++abi's strong definition routes this to std::terminate) wasm32-hwjs: __libc_dlsym reached without a dynamic loader (no __libc_dlopen ever succeeds here) wasm32-hwjs: __libc_dlclose reached without a dynamic loader (no __libc_dlopen ever succeeds here) hwjs-user-rt VIOLATION[lane %u]: RT op on UNOCCUPIED lane %u (occupancy bitmap %x, lane generation %u) — the driver skipped __hwjs_lane_attach, or attached, detached and kept running (stale lane binding); lane exclusivity is protocol soundness (two Workers on one lane would otherwise be invisible to every per-lane guard) hwjs-user-rt VIOLATION[lane %u]: lane_assert_gen on UNOCCUPIED lane %u (gen %u matches but the lane is detached) pmu: %s event%d: %s :: numasks too big (<%d) pmu: %s event%d: %s :: overflow umask idx defined but not needed (<%d) pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d) hwjs-user-rt VIOLATION[lane %u]: drive-loop PROGRESS backstop tripped (wedged handle %px id-via-frame-header[h+4]=%px) — %u consecutive zero-progress resume slices past stall_bound=%u; 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pfm_arm_detect_hisilicon_kunpeng(pfm_arm_detect_hisilicon_kunpeng.destroy'pfm_arm_detect_hisilicon_kunpeng.resumepfm_arm_detect_n1pfm_arm_detect_n1.destroypfm_arm_detect_n1.resumepfm_arm_detect_v1pfm_arm_detect_v1.destroypfm_arm_detect_v1.resumepfm_tx2_unc_get_event_encoding&pfm_tx2_unc_get_event_encoding.destroy%pfm_tx2_unc_get_event_encoding.resumepfm_tx2_unc_get_perf_encoding%pfm_tx2_unc_get_perf_encoding.destroy$pfm_tx2_unc_get_perf_encoding.resume"pfm_kunpeng_unc_get_event_encoding*pfm_kunpeng_unc_get_event_encoding.destroy)pfm_kunpeng_unc_get_event_encoding.resume!pfm_kunpeng_unc_get_perf_encoding)pfm_kunpeng_unc_get_perf_encoding.destroy(pfm_kunpeng_unc_get_perf_encoding.resumepfmlib_raw_pmu_detectpfmlib_raw_pmu_encodepfmlib_raw_pmu_encode.destroypfmlib_raw_pmu_encode.resumepfmlib_parse_eventpfmlib_parse_event.destroypfmlib_parse_event.resumepfmlib_build_fstrpfmlib_build_fstr.destroypfmlib_build_fstr.resume match_eventmatch_event.destroymatch_event.resumepfmlib_build_event_pattrs!pfmlib_build_event_pattrs.destroy pfmlib_build_event_pattrs.resumepfmlib_parse_event_attrpfmlib_parse_event_attr.destroypfmlib_parse_event_attr.resumepfmlib_sanitize_eventpfmlib_sanitize_event.destroypfmlib_sanitize_event.resume pfmlib_getlpfmlib_getl.destroypfmlib_getl.resumepfmlib_compact_pattrspfmlib_compact_pattrs.destroypfmlib_compact_pattrs.resumepfmlib_check_structpfmlib_check_struct.destroypfmlib_check_struct.resumepfm_initializepfm_initialize.destroypfm_initialize.resume pfm_terminatepfm_terminate.destroypfm_terminate.resumepfmlib_release_eventpfmlib_release_event.destroypfmlib_release_event.resumepfm_get_event_nextpfm_get_event_next.destroypfm_get_event_next.resumepfm_get_os_event_encoding!pfm_get_os_event_encoding.destroy pfm_get_os_event_encoding.resumepfm_get_event_infopfm_get_event_info.destroypfm_get_event_info.resumepfm_get_pmu_infopfm_get_pmu_info.destroypfm_get_pmu_info.resumepfmlib_get_pmu_by_typepfmlib_get_pmu_by_type.destroypfmlib_get_pmu_by_type.resumepfmlib_sort_attrpfmlib_sort_attr.destroypfmlib_sort_attr.resumepfmlib_compare_attr_idpfm_arm_detect_n2pfm_arm_detect_n2.destroypfm_arm_detect_n2.resumepfm_arm_detect_v2pfm_arm_detect_v2.destroypfm_arm_detect_v2.resumepfm_arm_get_perf_encoding!pfm_arm_get_perf_encoding.destroy pfm_arm_get_perf_encoding.resumepfm_arm_perf_validate_pattrs$pfm_arm_perf_validate_pattrs.destroy#pfm_arm_perf_validate_pattrs.resumepfm_perf_event_os_detect pfm_perf_event_os_detect.destroypfm_perf_event_os_detect.resumeperf_get_os_attr_infoperf_get_os_attr_info.destroyperf_get_os_attr_info.resumeperf_get_os_nattrsperf_get_os_nattrs.destroyperf_get_os_nattrs.resumepfmlib_perf_event_encode pfmlib_perf_event_encode.destroypfmlib_perf_event_encode.resumepfm_perf_raw_detectpfm_perf_raw_detect.destroypfm_perf_raw_detect.resumepfm_perf_raw_get_event_firstpfm_perf_raw_get_event_nextpfm_perf_raw_get_event_infopfm_perf_raw_get_event_nattrspfm_perf_raw_event_is_valid pfm_perf_raw_get_event_attr_infopfm_perf_raw_get_encoding!pfm_perf_raw_get_encoding.destroy pfm_perf_raw_get_encoding.resumepfm_perf_raw_get_perf_encoding!pfm_perf_raw_perf_validate_pattrspfm_perf_raw_match_event pfm_perf_raw_match_event.destroypfm_perf_raw_match_event.resume__libc_assert_fail__libc_assert_fail.destroy__libc_assert_fail.resume__libc_check_standard_fds!__libc_check_standard_fds.destroy __libc_check_standard_fds.resume check_one_fdcheck_one_fd.destroycheck_one_fd.resume__libc_init_first__libc_init_first.destroy__libc_init_first.resume call_finicall_fini.destroycall_fini.resume call_initcall_init.destroycall_init.resume__libc_start_call_main__libc_start_call_main.destroy__libc_start_call_main.resume__libc_setup_tls__libc_setup_tls.destroy__libc_setup_tls.resume __chk_fail__chk_fail.destroy__chk_fail.resume__fortify_fail__fortify_fail.destroy__fortify_fail.resume__readonly_area__readonly_area.destroy__readonly_area.resume__readonly_area_fallback __readonly_area_fallback.destroy__readonly_area_fallback.resume __closedir__closedir.destroy__closedir.resume__dirfd __fdopendir__fdopendir.destroy__fdopendir.resume __getdents64__getdents64.destroy__getdents64.resume opendir_tailopendir_tail.destroyopendir_tail.resume __opendir__opendir.destroy__opendir.resume __alloc_dir__alloc_dir.destroy__alloc_dir.resume __readdir64__readdir64.destroy__readdir64.resume __rewinddir__rewinddir.destroy__rewinddir.resume _dlerror_run_dlerror_run.destroy_dlerror_run.resume__dlopen__dlopen.destroy__dlopen.resume dlopen_doitdlopen_doit.destroydlopen_doit.resume_dl_addr_inside_object_dl_addr_inside_object.destroy_dl_addr_inside_object.resume fatal_errorfatal_error.destroyfatal_error.resume_dl_signal_error_dl_signal_error.destroy_dl_signal_error.resume_dl_catch_exception_dl_catch_exception.destroy_dl_catch_exception.resume_dl_catch_error_dl_catch_error.destroy_dl_catch_error.resume_dl_debug_state_dl_early_allocate__sbrk_dl_error_free_dl_error_free.destroy_dl_error_free.resume_dl_exception_create_dl_exception_create.destroy_dl_exception_create.resume_dl_find_object_dl_find_object.destroy_dl_find_object.resume_dl_find_object_slow_dl_find_object_slow.destroy_dl_find_object_slow.resume __libc_dlsym__libc_dlsym.destroy__libc_dlsym.resume__libc_dlclose__libc_dlclose.destroy__libc_dlclose.resume _dl_strtoul_dl_strtoul.destroy_dl_strtoul.resume_dl_open_dl_open.destroy_dl_open.resume_dl_debug_vdprintf_dl_debug_vdprintf.destroy_dl_debug_vdprintf.resume_dl_debug_strlen_dl_debug_strlen.resume_dl_debug_strlen.destroy_dl_readonly_area_dl_readonly_area.destroy_dl_readonly_area.resumeelf_machine_matches_host_dl_non_dynamic_init_dl_non_dynamic_init.destroy_dl_non_dynamic_init.resume_dl_tls_static_surplus_init#_dl_tls_static_surplus_init.destroy"_dl_tls_static_surplus_init.resume_dl_determine_tlsoffset_dl_determine_tlsoffset.destroy_dl_determine_tlsoffset.resume_dl_allocate_tls_init_dl_allocate_tls_init.destroy_dl_allocate_tls_init.resumeoom oom.destroy oom.resume __tls_init_tp__tls_init_tp.destroy__tls_init_tp.resume__tunables_init__tunables_init.destroy__tunables_init.resume _dl_strlen_dl_strlen.resume_dl_strlen.destroy__tunable_get_val__tunable_get_val.destroy__tunable_get_val.resume__libc_early_init__libc_early_init.destroy__libc_early_init.resume__gconv__gconv.destroy__gconv.resume__gconv_get_builtin_trans!__gconv_get_builtin_trans.destroy __gconv_get_builtin_trans.resume__gconv_load_cache__gconv_load_cache.destroy__gconv_load_cache.resume__gconv_lookup_cache__gconv_lookup_cache.destroy__gconv_lookup_cache.resume find_modulefind_module.destroyfind_module.resume__gconv_release_cache__gconv_release_cache.destroy__gconv_release_cache.resume__gconv_create_spec__gconv_create_spec.destroy__gconv_create_spec.resumegconv_parse_codegconv_parse_code.destroygconv_parse_code.resume__gconv_destroy_spec__gconv_destroy_spec.destroy__gconv_destroy_spec.resume__gconv_load_conf__gconv_load_conf.destroy__gconv_load_conf.resume__gconv_read_conf__gconv_read_conf.destroy__gconv_read_conf.resume__gconv_get_path__gconv_get_path.destroy__gconv_get_path.resumeread_conf_fileread_conf_file.destroyread_conf_file.resume insert_moduleinsert_module.destroyinsert_module.resume add_alias2add_alias2.destroyadd_alias2.resume add_moduleadd_module.destroyadd_module.resume__gconv_alias_compare__gconv_alias_compare.destroy__gconv_alias_compare.resume__gconv_release_step__gconv_release_step.destroy__gconv_release_step.resume__gconv_find_transform__gconv_find_transform.destroy__gconv_find_transform.resumefind_derivationfind_derivation.destroyfind_derivation.resumederivation_comparederivation_compare.destroyderivation_compare.resume__gconv_close_transform__gconv_close_transform.destroy__gconv_close_transform.resume__gconv_find_shlib__gconv_find_shlib.destroy__gconv_find_shlib.resume known_compareknown_compare.destroyknown_compare.resumedo_release_shlibdo_release_shlib.destroydo_release_shlib.resume__gconv_release_shlib__gconv_release_shlib.destroy__gconv_release_shlib.resume __gconv_open__gconv_open.destroy__gconv_open.resume__gconv_btwoc_ascii__gconv_transform_internal_ucs4'__gconv_transform_internal_ucs4.destroy&__gconv_transform_internal_ucs4.resume__gconv_transform_ucs4_internal'__gconv_transform_ucs4_internal.destroy&__gconv_transform_ucs4_internal.resume!__gconv_transform_internal_ucs4le)__gconv_transform_internal_ucs4le.destroy(__gconv_transform_internal_ucs4le.resume!__gconv_transform_ucs4le_internal)__gconv_transform_ucs4le_internal.destroy(__gconv_transform_ucs4le_internal.resume __gconv_transform_ascii_internal(__gconv_transform_ascii_internal.destroy'__gconv_transform_ascii_internal.resume __gconv_transform_internal_ascii(__gconv_transform_internal_ascii.destroy'__gconv_transform_internal_ascii.resume__gconv_transform_internal_utf8'__gconv_transform_internal_utf8.destroy&__gconv_transform_internal_utf8.resume__gconv_transform_utf8_internal'__gconv_transform_utf8_internal.destroy&__gconv_transform_utf8_internal.resume__gconv_transform_ucs2_internal'__gconv_transform_ucs2_internal.destroy&__gconv_transform_ucs2_internal.resume__gconv_transform_internal_ucs2'__gconv_transform_internal_ucs2.destroy&__gconv_transform_internal_ucs2.resume&__gconv_transform_ucs2reverse_internal.__gconv_transform_ucs2reverse_internal.destroy-__gconv_transform_ucs2reverse_internal.resume&__gconv_transform_internal_ucs2reverse.__gconv_transform_internal_ucs2reverse.destroy-__gconv_transform_internal_ucs2reverse.resume__gconv_transliterate__gconv_transliterate.destroy__gconv_transliterate.resume __dcgettext__dcgettext.destroy__dcgettext.resume __dcigettext__dcigettext.destroy__dcigettext.resumetranscmptranscmp.destroytranscmp.resume plural_evalplural_eval.destroyplural_eval.resume _nl_find_msg_nl_find_msg.destroy_nl_find_msg.resume_nl_explode_name_nl_explode_name.destroy_nl_explode_name.resume_nl_find_domain_nl_find_domain.destroy_nl_find_domain.resume __hash_string__hash_string.destroy__hash_string.resume_nl_make_l10nflist_nl_make_l10nflist.destroy_nl_make_l10nflist.resume_nl_normalize_codeset_nl_normalize_codeset.destroy_nl_normalize_codeset.resume_nl_load_domain_nl_load_domain.destroy_nl_load_domain.resumeget_sysdep_segment_value get_sysdep_segment_value.destroyget_sysdep_segment_value.resume_nl_expand_alias_nl_expand_alias.destroy_nl_expand_alias.resume alias_comparealias_compare.destroyalias_compare.resume__gettextparse__gettextparse.destroy__gettextparse.resume__gettext_free_exp__gettext_free_exp.destroy__gettext_free_exp.resume__gettext_extract_plural __gettext_extract_plural.destroy__gettext_extract_plural.resume__access__access.destroy__access.resume__close__close.destroy__close.resume__close_nocancel__close_nocancel.destroy__close_nocancel.resume__close_nocancel_nostatus__fcntl64_nocancel_adjusted#__fcntl64_nocancel_adjusted.destroy"__fcntl64_nocancel_adjusted.resume __fstat64__fstat64.destroy__fstat64.resume __fstatat64__fstatat64.destroy__fstatat64.resume__getcwd__getcwd.destroy__getcwd.resume __lseek64__lseek64.destroy__lseek64.resume __lstat64__lstat64.destroy__lstat64.resume__pread64_nocancel__pread64_nocancel.destroy__pread64_nocancel.resume __libc_read__libc_read.destroy__libc_read.resume__read_nocancel__read_nocancel.destroy__read_nocancel.resume__stat64__stat64.destroy__stat64.resume __libc_write__libc_write.destroy__libc_write.resume__write_nocancel__write_nocancel.destroy__write_nocancel.resume_IO_file_doallocate_IO_file_doallocate.destroy_IO_file_doallocate.resume_IO_new_file_init_internal"_IO_new_file_init_internal.destroy!_IO_new_file_init_internal.resume_IO_new_file_close_it_IO_new_file_close_it.destroy_IO_new_file_close_it.resume_IO_new_do_write_IO_new_do_write.destroy_IO_new_do_write.resume new_do_writenew_do_write.destroynew_do_write.resume_IO_new_file_finish_IO_new_file_finish.destroy_IO_new_file_finish.resume _IO_file_open_IO_file_open.destroy_IO_file_open.resume_IO_new_file_fopen_IO_new_file_fopen.destroy_IO_new_file_fopen.resume_IO_new_file_setbuf_IO_new_file_setbuf.destroy_IO_new_file_setbuf.resume_IO_file_setbuf_mmap_IO_file_setbuf_mmap.destroy_IO_file_setbuf_mmap.resume_IO_new_file_underflow_IO_new_file_underflow.destroy_IO_new_file_underflow.resume_IO_file_underflow_mmap_IO_file_underflow_mmap.destroy_IO_file_underflow_mmap.resumemmap_remap_checkmmap_remap_check.destroymmap_remap_check.resume_IO_file_underflow_maybe_mmap%_IO_file_underflow_maybe_mmap.destroy$_IO_file_underflow_maybe_mmap.resumedecide_maybe_mmapdecide_maybe_mmap.destroydecide_maybe_mmap.resume_IO_new_file_overflow_IO_new_file_overflow.destroy_IO_new_file_overflow.resume_IO_new_file_sync_IO_new_file_sync.destroy_IO_new_file_sync.resume_IO_file_sync_mmap_IO_file_sync_mmap.destroy_IO_file_sync_mmap.resume_IO_new_file_seekoff_IO_new_file_seekoff.destroy_IO_new_file_seekoff.resume_IO_file_seekoff_mmap_IO_file_seekoff_mmap.destroy_IO_file_seekoff_mmap.resume_IO_file_seekoff_maybe_mmap#_IO_file_seekoff_maybe_mmap.destroy"_IO_file_seekoff_maybe_mmap.resume _IO_file_read_IO_file_read.destroy_IO_file_read.resume _IO_file_seek_IO_file_seek.destroy_IO_file_seek.resume _IO_file_stat_IO_file_stat.destroy_IO_file_stat.resume_IO_file_close_mmap_IO_file_close_mmap.destroy_IO_file_close_mmap.resume_IO_file_close_IO_file_close.destroy_IO_file_close.resume_IO_new_file_write_IO_new_file_write.destroy_IO_new_file_write.resume_IO_new_file_xsputn_IO_new_file_xsputn.destroy_IO_new_file_xsputn.resume_IO_file_xsgetn_IO_file_xsgetn.destroy_IO_file_xsgetn.resume_IO_file_xsgetn_mmap_IO_file_xsgetn_mmap.destroy_IO_file_xsgetn_mmap.resume_IO_file_xsgetn_maybe_mmap"_IO_file_xsgetn_maybe_mmap.destroy!_IO_file_xsgetn_maybe_mmap.resume _IO_un_link_IO_un_link.destroy_IO_un_link.resume flush_cleanup__lll_lock_wake_private _IO_link_in_IO_link_in.destroy_IO_link_in.resume_IO_switch_to_get_mode_IO_switch_to_get_mode.destroy_IO_switch_to_get_mode.resume_IO_free_backup_area_IO_free_backup_area.destroy_IO_free_backup_area.resume __overflow__overflow.destroy__overflow.resume __underflow__underflow.destroy__underflow.resumesave_for_backupsave_for_backup.destroysave_for_backup.resume__uflow__uflow.destroy__uflow.resume_IO_setb_IO_setb.destroy_IO_setb.resume_IO_doallocbuf_IO_doallocbuf.destroy_IO_doallocbuf.resume_IO_default_uflow_IO_default_uflow.destroy_IO_default_uflow.resume_IO_default_xsputn_IO_default_xsputn.destroy_IO_default_xsputn.resume_IO_default_xsgetn_IO_default_xsgetn.destroy_IO_default_xsgetn.resume_IO_default_setbuf_IO_default_setbuf.destroy_IO_default_setbuf.resume_IO_default_seekpos_IO_default_seekpos.destroy_IO_default_seekpos.resume_IO_default_doallocate_IO_default_doallocate.destroy_IO_default_doallocate.resume_IO_default_sync_IO_default_finish_IO_default_finish.destroy_IO_default_finish.resume _IO_sputbackc_IO_sputbackc.destroy_IO_sputbackc.resume_IO_adjust_column_IO_adjust_column.destroy_IO_adjust_column.resume _IO_flush_all_IO_flush_all.destroy_IO_flush_all.resume _IO_cleanup_IO_cleanup.destroy_IO_cleanup.resume_IO_unsave_markers_IO_unsave_markers.destroy_IO_unsave_markers.resume_IO_default_pbackfail_IO_default_pbackfail.destroy_IO_default_pbackfail.resume_IO_default_seek_IO_default_stat_IO_default_read_IO_default_write_IO_default_showmanyc_IO_default_imbue_IO_getc_IO_getc.destroy_IO_getc.resume_IO_new_fclose_IO_new_fclose.destroy_IO_new_fclose.resume__fopen_internal__fopen_internal.destroy__fopen_internal.resume _IO_new_fopen_IO_new_fopen.destroy_IO_new_fopen.resume_IO_cookie_read_IO_cookie_read.destroy_IO_cookie_read.resume_IO_cookie_write_IO_cookie_write.destroy_IO_cookie_write.resume_IO_cookie_seek_IO_cookie_seek.destroy_IO_cookie_seek.resume_IO_cookie_close_IO_cookie_close.destroy_IO_cookie_close.resume_IO_cookie_seekoff_IO_cookie_seekoff.destroy_IO_cookie_seekoff.resume _IO_fwide_IO_fwide.destroy_IO_fwide.resume__libio_codecvt_out__libio_codecvt_out.destroy__libio_codecvt_out.resume__libio_codecvt_in__libio_codecvt_in.destroy__libio_codecvt_in.resume__libio_codecvt_length__libio_codecvt_length.destroy__libio_codecvt_length.resume __getdelim__getdelim.destroy__getdelim.resume _IO_getline_IO_getline.destroy_IO_getline.resume_IO_getline_info_IO_getline_info.destroy_IO_getline_info.resumeunlock_IO_new_proc_close_IO_new_proc_close.destroy_IO_new_proc_close.resume__printf_buffer_flush_dprintf%__printf_buffer_flush_dprintf.destroy$__printf_buffer_flush_dprintf.resume__vsprintf_internal__vsprintf_internal.destroy__vsprintf_internal.resume __libc_fatal__libc_fatal.destroy__libc_fatal.resume _IO_mem_sync_IO_mem_sync.destroy_IO_mem_sync.resume_IO_mem_finish_IO_mem_finish.destroy_IO_mem_finish.resume__printf_buffer_flush_obstack%__printf_buffer_flush_obstack.destroy$__printf_buffer_flush_obstack.resume_IO_stdfiles_init_IO_stdfiles_init.destroy_IO_stdfiles_init.resume_IO_str_overflow_IO_str_overflow.destroy_IO_str_overflow.resume_IO_str_underflow_IO_str_seekoff_IO_str_seekoff.destroy_IO_str_seekoff.resumeenlarge_userbufenlarge_userbuf.destroyenlarge_userbuf.resume_IO_str_pbackfail_IO_str_pbackfail.destroy_IO_str_pbackfail.resume_IO_str_finish_IO_str_finish.destroy_IO_str_finish.resume__printf_buffer_flush_asprintf&__printf_buffer_flush_asprintf.destroy%__printf_buffer_flush_asprintf.resume__vasprintf_internal__vasprintf_internal.destroy__vasprintf_internal.resume__vsnprintf_internal__vsnprintf_internal.destroy__vsnprintf_internal.resume ___vsnprintf___vsnprintf.destroy___vsnprintf.resume_IO_vtable_check_IO_vtable_check.destroy_IO_vtable_check.resume_IO_wfile_doallocate_IO_wfile_doallocate.destroy_IO_wfile_doallocate.resume _IO_wdo_write_IO_wdo_write.destroy_IO_wdo_write.resume_IO_wfile_underflow_IO_wfile_underflow.destroy_IO_wfile_underflow.resume_IO_wfile_underflow_mmap _IO_wfile_underflow_mmap.destroy_IO_wfile_underflow_mmap.resume_IO_wfile_underflow_maybe_mmap&_IO_wfile_underflow_maybe_mmap.destroy%_IO_wfile_underflow_maybe_mmap.resume_IO_wfile_overflow_IO_wfile_overflow.destroy_IO_wfile_overflow.resume_IO_wfile_sync_IO_wfile_sync.destroy_IO_wfile_sync.resume_IO_wfile_seekoff_IO_wfile_seekoff.destroy_IO_wfile_seekoff.resumeadjust_wide_dataadjust_wide_data.destroyadjust_wide_data.resume_IO_wfile_xsputn_IO_wfile_xsputn.destroy_IO_wfile_xsputn.resume _IO_wsetb_IO_wsetb.destroy_IO_wsetb.resume_IO_wdefault_pbackfail_IO_wdefault_pbackfail.destroy_IO_wdefault_pbackfail.resumesave_for_wbackupsave_for_wbackup.destroysave_for_wbackup.resume_IO_wdefault_finish_IO_wdefault_finish.destroy_IO_wdefault_finish.resume_IO_wdefault_uflow_IO_wdefault_uflow.destroy_IO_wdefault_uflow.resume_IO_switch_to_wget_mode_IO_switch_to_wget_mode.destroy_IO_switch_to_wget_mode.resume_IO_free_wbackup_area_IO_free_wbackup_area.destroy_IO_free_wbackup_area.resume __wunderflow__wunderflow.destroy__wunderflow.resume_IO_wdefault_xsputn_IO_wdefault_xsputn.destroy_IO_wdefault_xsputn.resume_IO_wdefault_xsgetn_IO_wdefault_xsgetn.destroy_IO_wdefault_xsgetn.resume_IO_wdoallocbuf_IO_wdoallocbuf.destroy_IO_wdoallocbuf.resume_IO_wdefault_doallocate_IO_wdefault_doallocate.destroy_IO_wdefault_doallocate.resume _IO_wmem_sync_IO_wmem_sync.destroy_IO_wmem_sync.resume_IO_wmem_finish_IO_wmem_finish.destroy_IO_wmem_finish.resume_IO_wstr_overflow_IO_wstr_overflow.destroy_IO_wstr_overflow.resume_IO_wstr_underflow_IO_wstr_seekoff_IO_wstr_seekoff.destroy_IO_wstr_seekoff.resumeenlarge_userbuf.2456enlarge_userbuf.2456.destroyenlarge_userbuf.2456.resume_IO_wstr_pbackfail_IO_wstr_pbackfail.destroy_IO_wstr_pbackfail.resume_IO_wstr_finish_IO_wstr_finish.destroy_IO_wstr_finish.resume__ptmalloc_init__ptmalloc_init.destroy__ptmalloc_init.resume_dl_tunable_set_top_pad_dl_tunable_set_perturb_byte_dl_tunable_set_mmap_threshold_dl_tunable_set_trim_threshold_dl_tunable_set_mmaps_max_dl_tunable_set_arena_max_dl_tunable_set_arena_test_dl_tunable_set_tcache_max_dl_tunable_set_tcache_count%_dl_tunable_set_tcache_unsorted_limit_dl_tunable_set_hugetlb_dl_tunable_set_hugetlb.destroy_dl_tunable_set_hugetlb.resumemalloc_printerrmalloc_printerr.destroymalloc_printerr.resume_int_free_chunk_int_free_chunk.destroy_int_free_chunk.resume_int_free_merge_chunk_int_free_merge_chunk.destroy_int_free_merge_chunk.resume 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__strtoul_internal.resume __isoc23_strtoul __isoc23_strtoul.destroy __isoc23_strtoul.resume ____strtoul_l_internal ____strtoul_l_internal.destroy ____strtoul_l_internal.resume __strtoull_internal __strtoull_internal.destroy __strtoull_internal.resume __strtoull __strtoull.destroy __strtoull.resume ____strtoull_l_internal ____strtoull_l_internal.destroy ____strtoull_l_internal.resume __mpn_submul_1 __mpn_submul_1.destroy __mpn_submul_1.resume __mpn_sub_n __mpn_sub_n.destroy __mpn_sub_n.resume __argz_next __argz_next.destroy __argz_next.resume __memchr __memchr.destroy __memchr.resume memcpy memcpy.destroy memcpy.resume __memrchr __memrchr.destroy __memrchr.resume memset memset.destroy memset.resume __stpcpy.destroy __stpcpy.resume __strcasecmp __strcasecmp.destroy __strcasecmp.resume __strcasecmp_l __strcasecmp_l.destroy __strcasecmp_l.resume strchr strchr.destroy strchr.resume __strchrnul __strchrnul.destroy __strchrnul.resume strcmp strcmp.destroy strcmp.resume strcpy strcpy.destroy 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