// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: -target-feature +zvfh -disable-O0-optnone \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: FileCheck --check-prefix=CHECK-RV64 %s #include // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m // CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr [[BASE]], [[MASK]], i64 [[VL]], i64 3, i64 6) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 3) [[TMP1]] // vfloat64m1x3_t test_vlseg3e64ff_v_f64m1x3_m(vbool64_t mask, const double *base, size_t *new_vl, size_t vl) { return __riscv_vlseg3e64ff(mask, base, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m // CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr [[BASE]], [[MASK]], i64 [[VL]], i64 3, i64 6) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 3) [[TMP1]] // vfloat64m2x3_t test_vlseg3e64ff_v_f64m2x3_m(vbool32_t mask, const double *base, size_t *new_vl, size_t vl) { return __riscv_vlseg3e64ff(mask, base, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_m // CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr [[BASE]], [[MASK]], i64 [[VL]], i64 3, i64 6) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 3) [[TMP1]] // vint64m1x3_t test_vlseg3e64ff_v_i64m1x3_m(vbool64_t mask, const int64_t *base, size_t *new_vl, size_t vl) { return __riscv_vlseg3e64ff(mask, base, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_m // CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr [[BASE]], [[MASK]], i64 [[VL]], i64 3, i64 6) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 3) [[TMP1]] // vint64m2x3_t test_vlseg3e64ff_v_i64m2x3_m(vbool32_t mask, const int64_t *base, size_t *new_vl, size_t vl) { return __riscv_vlseg3e64ff(mask, base, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_m // CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr [[BASE]], [[MASK]], i64 [[VL]], i64 3, i64 6) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 3) [[TMP1]] // vuint64m1x3_t test_vlseg3e64ff_v_u64m1x3_m(vbool64_t mask, const uint64_t *base, size_t *new_vl, size_t vl) { return __riscv_vlseg3e64ff(mask, base, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_m // CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr [[BASE]], [[MASK]], i64 [[VL]], i64 3, i64 6) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 3), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 3) [[TMP1]] // vuint64m2x3_t test_vlseg3e64ff_v_u64m2x3_m(vbool32_t mask, const uint64_t *base, size_t *new_vl, size_t vl) { return __riscv_vlseg3e64ff(mask, base, new_vl, vl); }