// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \ // RUN: -target-feature +zvfbfmin -disable-O0-optnone \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: FileCheck --check-prefix=CHECK-RV64 %s #include // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu( // CHECK-RV64-SAME: target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], i64 [[VL]], i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tu(vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu( // CHECK-RV64-SAME: target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], i64 [[VL]], i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tu(vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu( // CHECK-RV64-SAME: target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], i64 [[VL]], i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tu(vbfloat16m1x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tu(vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tum(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tum(vm, vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tum(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tum(vm, vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tum(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tum(vm, vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tumu( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tumu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tumu(vm, vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tumu( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tumu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tumu(vm, vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tumu( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tumu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_tumu(vm, vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_mu( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_mu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_mu(vm, vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_mu( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_mu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_mu(vm, vd, rs1, new_vl, vl); } // CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_mu( // CHECK-RV64-SAME: [[VM:%.*]], target("riscv.vector.tuple", , 6) [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1, i64 4) // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { target("riscv.vector.tuple", , 6), i64 } [[TMP0]], 1 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 // CHECK-RV64-NEXT: ret target("riscv.vector.tuple", , 6) [[TMP1]] // vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { return __riscv_vlseg6e16ff_mu(vm, vd, rs1, new_vl, vl); }