; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=aarch64 -mattr=+v8.2a,+fullfp16  | FileCheck %s

declare <4 x half> @llvm.nearbyint.v4f16(<4 x half>)
declare <8 x half> @llvm.nearbyint.v8f16(<8 x half>)
declare <4 x half> @llvm.sqrt.v4f16(<4 x half>)
declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtzs.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtzu.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtas.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtau.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtms.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtmu.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtns.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtnu.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtps.v4i16.v4f16(<4 x half>)
declare <4 x i16> @llvm.aarch64.neon.fcvtpu.v4i16.v4f16(<4 x half>)

define dso_local <4 x half> @t_vrndi_f16(<4 x half> %a) {
; CHECK-LABEL: t_vrndi_f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    frinti v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vrndi1.i = tail call <4 x half> @llvm.nearbyint.v4f16(<4 x half> %a)
  ret <4 x half> %vrndi1.i
}

define dso_local <8 x half> @t_vrndiq_f16(<8 x half> %a) {
; CHECK-LABEL: t_vrndiq_f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    frinti v0.8h, v0.8h
; CHECK-NEXT:    ret
entry:
  %vrndi1.i = tail call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %a)
  ret <8 x half> %vrndi1.i
}

define dso_local <4 x half> @t_vsqrt_f16(<4 x half> %a) {
; CHECK-LABEL: t_vsqrt_f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fsqrt v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vsqrt.i = tail call <4 x half> @llvm.sqrt.v4f16(<4 x half> %a)
  ret <4 x half> %vsqrt.i
}

define dso_local <8 x half> @t_vsqrtq_f16(<8 x half> %a) {
; CHECK-LABEL: t_vsqrtq_f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fsqrt v0.8h, v0.8h
; CHECK-NEXT:    ret
entry:
  %vsqrt.i = tail call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)
  ret <8 x half> %vsqrt.i
}

define <4 x i16> @t_fcvtzs_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtzs_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzs v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtzs.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtzu_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtzu_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtzu v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtzu.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtas_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtas_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtas v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtas.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtau_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtau_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtau v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtau.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtms_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtms_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtms v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtms.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtmu_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtmu_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtmu v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtmu.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtns_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtns_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtns v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtns.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtnu_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtnu_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtnu v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtnu.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtps_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtps_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtps v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtps.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}

define <4 x i16> @t_fcvtpu_v4i16_v4f16(<4 x half> %a) {
; CHECK-LABEL: t_fcvtpu_v4i16_v4f16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvtpu v0.4h, v0.4h
; CHECK-NEXT:    ret
entry:
  %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtpu.v4i16.v4f16(<4 x half> %a)
  ret <4 x i16> %vcvt
}