; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck --check-prefixes=GFX7 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12 %s

define amdgpu_ps void @store_uniform_P1_addr_i8(i8 %a, ptr addrspace(1) inreg %out) {
; GFX7-LABEL: store_uniform_P1_addr_i8:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    buffer_store_byte v0, off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX12-LABEL: store_uniform_P1_addr_i8:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v1, 0
; GFX12-NEXT:    global_store_b8 v1, v0, s[0:1]
; GFX12-NEXT:    s_endpgm
  store i8 %a, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @store_uniform_P1_addr_i16(i16 %a, ptr addrspace(1) inreg %out) {
; GFX7-LABEL: store_uniform_P1_addr_i16:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX12-LABEL: store_uniform_P1_addr_i16:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v1, 0
; GFX12-NEXT:    global_store_b16 v1, v0, s[0:1]
; GFX12-NEXT:    s_endpgm
  store i16 %a, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @store_uniform_P1_addr_i32(i32 %a, ptr addrspace(1) inreg %out) {
; GFX7-LABEL: store_uniform_P1_addr_i32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX12-LABEL: store_uniform_P1_addr_i32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v1, 0
; GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX12-NEXT:    s_endpgm
  store i32 %a, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @store_uniform_P1_addr_v2i32(<2 x i32> %a, ptr addrspace(1) inreg %out) {
; GFX7-LABEL: store_uniform_P1_addr_v2i32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX12-LABEL: store_uniform_P1_addr_v2i32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v2, 0
; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT:    s_endpgm
  store <2 x i32> %a, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @store_uniform_P1_addr_v3i32(<3 x i32> %a, ptr addrspace(1) inreg %out) {
; GFX7-LABEL: store_uniform_P1_addr_v3i32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX12-LABEL: store_uniform_P1_addr_v3i32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v3, 0
; GFX12-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
; GFX12-NEXT:    s_endpgm
  store <3 x i32> %a, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @store_uniform_P1_addr_v4i32(<4 x i32> %a, ptr addrspace(1) inreg %out) {
; GFX7-LABEL: store_uniform_P1_addr_v4i32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX12-LABEL: store_uniform_P1_addr_v4i32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v4, 0
; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
; GFX12-NEXT:    s_endpgm
  store <4 x i32> %a, ptr addrspace(1) %out
  ret void
}