; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s ; SGPR phi ends up with VGPR inputs. Make sure we do not try to ; process a copy which has already been erased (which was already ; inserted by the pass). define double @issue130646(i64 %arg) { ; CHECK-LABEL: issue130646: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: v_mov_b32_e32 v2, 0 ; CHECK-NEXT: v_mov_b32_e32 v3, 0 ; CHECK-NEXT: s_mov_b64 s[4:5], 0 ; CHECK-NEXT: s_branch .LBB0_2 ; CHECK-NEXT: .LBB0_1: ; %for.body.5 ; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: s_lshr_b64 s[6:7], s[4:5], 1 ; CHECK-NEXT: v_or_b32_e32 v3, s7, v3 ; CHECK-NEXT: v_or_b32_e32 v2, s6, v2 ; CHECK-NEXT: s_lshr_b64 s[6:7], s[4:5], 5 ; CHECK-NEXT: s_or_b32 s6, s6, 1 ; CHECK-NEXT: v_or3_b32 v3, v3, v1, s7 ; CHECK-NEXT: v_or3_b32 v2, v2, v0, s6 ; CHECK-NEXT: s_lshr_b64 s[4:5], s[4:5], 8 ; CHECK-NEXT: s_cbranch_execz .LBB0_4 ; CHECK-NEXT: .LBB0_2: ; %for.body ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: s_cmp_eq_u64 s[4:5], 0 ; CHECK-NEXT: v_readfirstlane_b32 s8, v0 ; CHECK-NEXT: v_readfirstlane_b32 s9, v1 ; CHECK-NEXT: s_cbranch_scc0 .LBB0_1 ; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CHECK-NEXT: s_mov_b64 s[4:5], s[8:9] ; CHECK-NEXT: .LBB0_4: ; %for.cond.cleanup ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: s_setpc_b64 s[30:31] entry: br label %for.body for.cond.cleanup: ; preds = %for.body %cmp3.not.i.i.i = icmp eq i64 %r.0108, 0 br i1 %cmp3.not.i.i.i, label %cleanup, label %if.end26.i.i if.end26.i.i: ; preds = %for.cond.cleanup br label %cleanup for.body: ; preds = %for.body.5, %entry %current_bit.01093 = phi i64 [ 0, %entry ], [ %shr.3.7, %for.body.5 ] %r.0108 = phi i64 [ 0, %entry ], [ %shl28.3.7, %for.body.5 ] %shr.3 = lshr i64 %current_bit.01093, 1 %i = or i64 %r.0108, %shr.3 %i3 = or i64 %i, %arg %tobool27.not.3.4 = icmp ult i64 %current_bit.01093, 1 br i1 %tobool27.not.3.4, label %for.cond.cleanup, label %for.body.5 for.body.5: ; preds = %for.body %shr.3.4 = lshr i64 %current_bit.01093, 5 %i6 = or i64 %shr.3.4, 1 %shl28.3.7 = or i64 %i6, %i3 %shr.3.7 = lshr i64 %current_bit.01093, 8 br label %for.body cleanup: ; preds = %if.end26.i.i, %for.cond.cleanup ret double 0.000000e+00 } define amdgpu_cs void @issue130119(i1 %arg) { ; CHECK-LABEL: issue130119: ; CHECK: ; %bb.0: ; %bb ; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v0 ; CHECK-NEXT: s_mov_b32 s16, 0 ; CHECK-NEXT: s_mov_b64 s[4:5], 0 ; CHECK-NEXT: s_branch .LBB1_2 ; CHECK-NEXT: .LBB1_1: ; %Flow2 ; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3] ; CHECK-NEXT: s_or_b64 s[4:5], s[2:3], s[4:5] ; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_cbranch_execz .LBB1_10 ; CHECK-NEXT: .LBB1_2: ; %bb1 ; CHECK-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NEXT: ; Child Loop BB1_4 Depth 2 ; CHECK-NEXT: s_and_b32 s2, s16, 1 ; CHECK-NEXT: s_cmp_eq_u32 s2, 0 ; CHECK-NEXT: s_cselect_b64 s[6:7], -1, 0 ; CHECK-NEXT: s_cmp_eq_u32 s2, 1 ; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3] ; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, v0 ; CHECK-NEXT: s_mov_b64 s[10:11], 0 ; CHECK-NEXT: ; implicit-def: $sgpr8_sgpr9 ; CHECK-NEXT: s_branch .LBB1_4 ; CHECK-NEXT: .LBB1_3: ; %Flow1 ; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2 ; CHECK-NEXT: s_xor_b64 s[14:15], s[14:15], -1 ; CHECK-NEXT: s_and_b64 s[12:13], exec, s[12:13] ; CHECK-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11] ; CHECK-NEXT: s_andn2_b64 s[8:9], s[8:9], exec ; CHECK-NEXT: s_and_b64 s[12:13], s[14:15], exec ; CHECK-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13] ; CHECK-NEXT: s_andn2_b64 exec, exec, s[10:11] ; CHECK-NEXT: s_cbranch_execz .LBB1_8 ; CHECK-NEXT: .LBB1_4: ; %bb3 ; CHECK-NEXT: ; Parent Loop BB1_2 Depth=1 ; CHECK-NEXT: ; => This Inner Loop Header: Depth=2 ; CHECK-NEXT: s_and_b64 vcc, exec, s[2:3] ; CHECK-NEXT: s_mov_b64 s[14:15], s[6:7] ; CHECK-NEXT: s_cbranch_vccnz .LBB1_6 ; CHECK-NEXT: ; %bb.5: ; %bb7 ; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2 ; CHECK-NEXT: s_mov_b64 s[14:15], -1 ; CHECK-NEXT: .LBB1_6: ; %Flow ; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2 ; CHECK-NEXT: s_mov_b64 s[12:13], -1 ; CHECK-NEXT: s_andn2_b64 vcc, exec, s[14:15] ; CHECK-NEXT: s_mov_b64 s[14:15], -1 ; CHECK-NEXT: s_cbranch_vccnz .LBB1_3 ; CHECK-NEXT: ; %bb.7: ; %bb8 ; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2 ; CHECK-NEXT: s_mov_b64 s[14:15], 0 ; CHECK-NEXT: s_orn2_b64 s[12:13], s[0:1], exec ; CHECK-NEXT: s_branch .LBB1_3 ; CHECK-NEXT: .LBB1_8: ; %loop.exit.guard ; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: s_or_b64 exec, exec, s[10:11] ; CHECK-NEXT: s_mov_b64 s[2:3], -1 ; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7] ; CHECK-NEXT: s_cbranch_execz .LBB1_1 ; CHECK-NEXT: ; %bb.9: ; %bb10 ; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: s_or_b32 s16, s16, 1 ; CHECK-NEXT: s_xor_b64 s[2:3], exec, -1 ; CHECK-NEXT: s_branch .LBB1_1 ; CHECK-NEXT: .LBB1_10: ; %DummyReturnBlock ; CHECK-NEXT: s_endpgm bb: br label %bb1 bb1: ; preds = %bb10, %bb %i = phi i32 [ 0, %bb ], [ %i11, %bb10 ] %i2 = phi i32 [ 0, %bb ], [ %i4, %bb10 ] br label %bb3 bb3: ; preds = %bb8, %bb1 %i4 = phi i32 [ %i2, %bb1 ], [ %i9, %bb8 ] %i5 = and i32 %i, 1 %i6 = icmp eq i32 %i5, 0 br i1 %i6, label %bb8, label %bb7 bb7: ; preds = %bb3 br label %bb8 bb8: ; preds = %bb7, %bb3 %i9 = phi i32 [ %i2, %bb3 ], [ 0, %bb7 ] br i1 %arg, label %bb10, label %bb3 bb10: ; preds = %bb8 %i11 = or i32 %i, 1 br label %bb1 }