; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX10-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1100 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX11-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX12-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250 %s

define amdgpu_kernel void @test_s_barrier() {
; GFX10-WGP-LABEL: test_s_barrier:
; GFX10-WGP:       ; %bb.0: ; %entry
; GFX10-WGP-NEXT:    s_barrier
; GFX10-WGP-NEXT:    s_endpgm
;
; GFX10-CU-LABEL: test_s_barrier:
; GFX10-CU:       ; %bb.0: ; %entry
; GFX10-CU-NEXT:    s_barrier
; GFX10-CU-NEXT:    s_endpgm
;
; GFX11-WGP-LABEL: test_s_barrier:
; GFX11-WGP:       ; %bb.0: ; %entry
; GFX11-WGP-NEXT:    s_barrier
; GFX11-WGP-NEXT:    s_endpgm
;
; GFX11-CU-LABEL: test_s_barrier:
; GFX11-CU:       ; %bb.0: ; %entry
; GFX11-CU-NEXT:    s_barrier
; GFX11-CU-NEXT:    s_endpgm
;
; GFX12-WGP-LABEL: test_s_barrier:
; GFX12-WGP:       ; %bb.0: ; %entry
; GFX12-WGP-NEXT:    s_barrier_signal -1
; GFX12-WGP-NEXT:    s_barrier_wait -1
; GFX12-WGP-NEXT:    s_endpgm
;
; GFX12-CU-LABEL: test_s_barrier:
; GFX12-CU:       ; %bb.0: ; %entry
; GFX12-CU-NEXT:    s_barrier_signal -1
; GFX12-CU-NEXT:    s_barrier_wait -1
; GFX12-CU-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_s_barrier:
; GFX1250:       ; %bb.0: ; %entry
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    s_barrier_signal -1
; GFX1250-NEXT:    s_barrier_wait -1
; GFX1250-NEXT:    s_endpgm
entry:
  call void @llvm.amdgcn.s.barrier()
  ret void
}

define amdgpu_kernel void @test_s_barrier_workgroup_fence() {
; GFX10-WGP-LABEL: test_s_barrier_workgroup_fence:
; GFX10-WGP:       ; %bb.0: ; %entry
; GFX10-WGP-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT:    s_barrier
; GFX10-WGP-NEXT:    s_endpgm
;
; GFX10-CU-LABEL: test_s_barrier_workgroup_fence:
; GFX10-CU:       ; %bb.0: ; %entry
; GFX10-CU-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-CU-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-CU-NEXT:    s_barrier
; GFX10-CU-NEXT:    s_endpgm
;
; GFX11-WGP-LABEL: test_s_barrier_workgroup_fence:
; GFX11-WGP:       ; %bb.0: ; %entry
; GFX11-WGP-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-WGP-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX11-WGP-NEXT:    s_barrier
; GFX11-WGP-NEXT:    s_endpgm
;
; GFX11-CU-LABEL: test_s_barrier_workgroup_fence:
; GFX11-CU:       ; %bb.0: ; %entry
; GFX11-CU-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-CU-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX11-CU-NEXT:    s_barrier
; GFX11-CU-NEXT:    s_endpgm
;
; GFX12-WGP-LABEL: test_s_barrier_workgroup_fence:
; GFX12-WGP:       ; %bb.0: ; %entry
; GFX12-WGP-NEXT:    s_wait_bvhcnt 0x0
; GFX12-WGP-NEXT:    s_wait_samplecnt 0x0
; GFX12-WGP-NEXT:    s_wait_storecnt 0x0
; GFX12-WGP-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-WGP-NEXT:    s_barrier_signal -1
; GFX12-WGP-NEXT:    s_barrier_wait -1
; GFX12-WGP-NEXT:    s_endpgm
;
; GFX12-CU-LABEL: test_s_barrier_workgroup_fence:
; GFX12-CU:       ; %bb.0: ; %entry
; GFX12-CU-NEXT:    s_wait_bvhcnt 0x0
; GFX12-CU-NEXT:    s_wait_samplecnt 0x0
; GFX12-CU-NEXT:    s_wait_storecnt 0x0
; GFX12-CU-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-CU-NEXT:    s_barrier_signal -1
; GFX12-CU-NEXT:    s_barrier_wait -1
; GFX12-CU-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_s_barrier_workgroup_fence:
; GFX1250:       ; %bb.0: ; %entry
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    s_wait_storecnt 0x0
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_barrier_signal -1
; GFX1250-NEXT:    s_barrier_wait -1
; GFX1250-NEXT:    s_endpgm
entry:
  fence syncscope("workgroup") release
  call void @llvm.amdgcn.s.barrier()
  ret void
}

define amdgpu_kernel void @test_s_barrier_agent_fence() {
; GFX10-WGP-LABEL: test_s_barrier_agent_fence:
; GFX10-WGP:       ; %bb.0: ; %entry
; GFX10-WGP-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT:    s_barrier
; GFX10-WGP-NEXT:    s_endpgm
;
; GFX10-CU-LABEL: test_s_barrier_agent_fence:
; GFX10-CU:       ; %bb.0: ; %entry
; GFX10-CU-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-CU-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-CU-NEXT:    s_barrier
; GFX10-CU-NEXT:    s_endpgm
;
; GFX11-WGP-LABEL: test_s_barrier_agent_fence:
; GFX11-WGP:       ; %bb.0: ; %entry
; GFX11-WGP-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-WGP-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX11-WGP-NEXT:    s_barrier
; GFX11-WGP-NEXT:    s_endpgm
;
; GFX11-CU-LABEL: test_s_barrier_agent_fence:
; GFX11-CU:       ; %bb.0: ; %entry
; GFX11-CU-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-CU-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX11-CU-NEXT:    s_barrier
; GFX11-CU-NEXT:    s_endpgm
;
; GFX12-WGP-LABEL: test_s_barrier_agent_fence:
; GFX12-WGP:       ; %bb.0: ; %entry
; GFX12-WGP-NEXT:    s_wait_bvhcnt 0x0
; GFX12-WGP-NEXT:    s_wait_samplecnt 0x0
; GFX12-WGP-NEXT:    s_wait_storecnt 0x0
; GFX12-WGP-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-WGP-NEXT:    s_barrier_signal -1
; GFX12-WGP-NEXT:    s_barrier_wait -1
; GFX12-WGP-NEXT:    s_endpgm
;
; GFX12-CU-LABEL: test_s_barrier_agent_fence:
; GFX12-CU:       ; %bb.0: ; %entry
; GFX12-CU-NEXT:    s_wait_bvhcnt 0x0
; GFX12-CU-NEXT:    s_wait_samplecnt 0x0
; GFX12-CU-NEXT:    s_wait_storecnt 0x0
; GFX12-CU-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-CU-NEXT:    s_barrier_signal -1
; GFX12-CU-NEXT:    s_barrier_wait -1
; GFX12-CU-NEXT:    s_endpgm
;
; GFX1250-LABEL: test_s_barrier_agent_fence:
; GFX1250:       ; %bb.0: ; %entry
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    global_wb scope:SCOPE_DEV
; GFX1250-NEXT:    s_wait_storecnt 0x0
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_barrier_signal -1
; GFX1250-NEXT:    s_barrier_wait -1
; GFX1250-NEXT:    s_endpgm
entry:
  fence syncscope("agent") release
  call void @llvm.amdgcn.s.barrier()
  ret void
}