; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx %s -o - | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s

;; xxvshuf4i.b
define <32 x i8> @shufflevector_xvshuf4i_v32i8(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: shufflevector_xvshuf4i_v32i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvshuf4i.b $xr0, $xr0, 27
; CHECK-NEXT:    ret
    %c = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12,
                                                               i32 19, i32 18, i32 17, i32 16, i32 23, i32 22, i32 21, i32 20, i32 27, i32 26, i32 25, i32 24, i32 31, i32 30, i32 29, i32 28>
    ret <32 x i8> %c
}

;; xvshuf4i.h
define <16 x i16> @shufflevector_xvshuf4i_v16i16(<16 x i16> %a, <16 x i16> %b) {
; CHECK-LABEL: shufflevector_xvshuf4i_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvshuf4i.h $xr0, $xr0, 27
; CHECK-NEXT:    ret
    %c = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
    ret <16 x i16> %c
}

;; xvshuf4i.w
define <8 x i32> @shufflevector_xvshuf4i_v8i32(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: shufflevector_xvshuf4i_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvshuf4i.w $xr0, $xr0, 27
; CHECK-NEXT:    ret
    %c = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
    ret <8 x i32> %c
}

;; xvshuf4i.d
define <4 x i64> @shufflevector_xvshuf4i_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK-LABEL: shufflevector_xvshuf4i_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvbsrl.v $xr0, $xr0, 8
; CHECK-NEXT:    xvbsll.v $xr1, $xr1, 8
; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
; CHECK-NEXT:    ret
    %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 4, i32 3, i32 6>
    ret <4 x i64> %c
}

;; xvshuf4i.w
define <8 x float> @shufflevector_xvshuf4i_v8f32(<8 x float> %a, <8 x float> %b) {
; CHECK-LABEL: shufflevector_xvshuf4i_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvshuf4i.w $xr0, $xr0, 27
; CHECK-NEXT:    ret
    %c = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
    ret <8 x float> %c
}

;; xvshuf4i.d
define <4 x double> @shufflevector_xvshuf4i_v4f64(<4 x double> %a, <4 x double> %b) {
; CHECK-LABEL: shufflevector_xvshuf4i_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI5_0)
; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI5_0)
; CHECK-NEXT:    xvshuf.d $xr2, $xr1, $xr0
; CHECK-NEXT:    xvori.b $xr0, $xr2, 0
; CHECK-NEXT:    ret
    %c = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
    ret <4 x double> %c
}