; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s

define <8 x float> @fadd_elt0_v8f32(float %a) nounwind {
; CHECK-LABEL: fadd_elt0_v8f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr1, -1168
; CHECK-NEXT:    fadd.s $fa0, $fa0, $fa1
; CHECK-NEXT:    ret
entry:
  %b = insertelement <8 x float> poison, float %a, i32 0
  %c = fadd <8 x float> %b, <float 1.0, float poison, float poison, float poison, float poison, float poison, float poison, float poison>
  ret <8 x float> %c
}

define <4 x double> @fadd_elt0_v4f64(double %a) nounwind {
; CHECK-LABEL: fadd_elt0_v4f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr1, -912
; CHECK-NEXT:    fadd.d $fa0, $fa0, $fa1
; CHECK-NEXT:    ret
entry:
  %b = insertelement <4 x double> poison, double %a, i32 0
  %c = fadd <4 x double> %b, <double 1.0, double poison, double poison, double poison>
  ret <4 x double> %c
}

define <8 x float> @fsub_splat_v8f32(float %a, float %b) nounwind {
; CHECK-LABEL: fsub_splat_v8f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fsub.s $fa0, $fa0, $fa1
; CHECK-NEXT:    xvreplve0.w $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %insa = insertelement <8 x float> poison, float %a, i32 0
  %insb = insertelement <8 x float> poison, float %b, i32 0
  %va = shufflevector <8 x float> %insa, <8 x float> poison, <8 x i32> zeroinitializer
  %vb = shufflevector <8 x float> %insb, <8 x float> poison, <8 x i32> zeroinitializer
  %c = fsub <8 x float> %va, %vb
  ret <8 x float> %c
}

define <4 x double> @fsub_splat_v4f64(double %a) nounwind {
; CHECK-LABEL: fsub_splat_v4f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vldi $vr1, -784
; CHECK-NEXT:    fadd.d $fa0, $fa0, $fa1
; CHECK-NEXT:    xvreplve0.d $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %insa = insertelement <4 x double> poison, double %a, i32 0
  %insb = insertelement <4 x double> poison, double 1.0, i32 0
  %va = shufflevector <4 x double> %insa, <4 x double> poison, <4 x i32> zeroinitializer
  %vb = shufflevector <4 x double> %insb, <4 x double> poison, <4 x i32> zeroinitializer
  %c = fsub <4 x double> %va, %vb
  ret <4 x double> %c
}