; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx %s -o - | FileCheck %s --check-prefix=LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s --check-prefix=LA64

define void @vec_reduce_add_v32i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v32i8:
; LA32:       # %bb.0:
; LA32-NEXT:    xvld $xr0, $a0, 0
; LA32-NEXT:    xvhaddw.h.b $xr0, $xr0, $xr0
; LA32-NEXT:    xvhaddw.w.h $xr0, $xr0, $xr0
; LA32-NEXT:    xvhaddw.d.w $xr0, $xr0, $xr0
; LA32-NEXT:    xvhaddw.q.d $xr0, $xr0, $xr0
; LA32-NEXT:    xvpermi.d $xr1, $xr0, 2
; LA32-NEXT:    xvadd.d $xr0, $xr1, $xr0
; LA32-NEXT:    xvpickve2gr.w $a0, $xr0, 0
; LA32-NEXT:    st.b $a0, $a1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: vec_reduce_add_v32i8:
; LA64:       # %bb.0:
; LA64-NEXT:    xvld $xr0, $a0, 0
; LA64-NEXT:    xvhaddw.h.b $xr0, $xr0, $xr0
; LA64-NEXT:    xvhaddw.w.h $xr0, $xr0, $xr0
; LA64-NEXT:    xvhaddw.d.w $xr0, $xr0, $xr0
; LA64-NEXT:    xvhaddw.q.d $xr0, $xr0, $xr0
; LA64-NEXT:    xvpermi.d $xr1, $xr0, 2
; LA64-NEXT:    xvadd.d $xr0, $xr1, $xr0
; LA64-NEXT:    xvpickve2gr.d $a0, $xr0, 0
; LA64-NEXT:    st.b $a0, $a1, 0
; LA64-NEXT:    ret
  %v = load <32 x i8>, ptr %src
  %res = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %v)
  store i8 %res, ptr %dst
  ret void
}

define void @vec_reduce_add_v16i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v16i16:
; LA32:       # %bb.0:
; LA32-NEXT:    xvld $xr0, $a0, 0
; LA32-NEXT:    xvhaddw.w.h $xr0, $xr0, $xr0
; LA32-NEXT:    xvhaddw.d.w $xr0, $xr0, $xr0
; LA32-NEXT:    xvhaddw.q.d $xr0, $xr0, $xr0
; LA32-NEXT:    xvpermi.d $xr1, $xr0, 2
; LA32-NEXT:    xvadd.d $xr0, $xr1, $xr0
; LA32-NEXT:    xvpickve2gr.w $a0, $xr0, 0
; LA32-NEXT:    st.h $a0, $a1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: vec_reduce_add_v16i16:
; LA64:       # %bb.0:
; LA64-NEXT:    xvld $xr0, $a0, 0
; LA64-NEXT:    xvhaddw.w.h $xr0, $xr0, $xr0
; LA64-NEXT:    xvhaddw.d.w $xr0, $xr0, $xr0
; LA64-NEXT:    xvhaddw.q.d $xr0, $xr0, $xr0
; LA64-NEXT:    xvpermi.d $xr1, $xr0, 2
; LA64-NEXT:    xvadd.d $xr0, $xr1, $xr0
; LA64-NEXT:    xvpickve2gr.d $a0, $xr0, 0
; LA64-NEXT:    st.h $a0, $a1, 0
; LA64-NEXT:    ret
  %v = load <16 x i16>, ptr %src
  %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %v)
  store i16 %res, ptr %dst
  ret void
}

define void @vec_reduce_add_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v8i32:
; LA32:       # %bb.0:
; LA32-NEXT:    xvld $xr0, $a0, 0
; LA32-NEXT:    xvhaddw.d.w $xr0, $xr0, $xr0
; LA32-NEXT:    xvhaddw.q.d $xr0, $xr0, $xr0
; LA32-NEXT:    xvpermi.d $xr1, $xr0, 2
; LA32-NEXT:    xvadd.d $xr0, $xr1, $xr0
; LA32-NEXT:    xvpickve2gr.w $a0, $xr0, 0
; LA32-NEXT:    st.w $a0, $a1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: vec_reduce_add_v8i32:
; LA64:       # %bb.0:
; LA64-NEXT:    xvld $xr0, $a0, 0
; LA64-NEXT:    xvhaddw.d.w $xr0, $xr0, $xr0
; LA64-NEXT:    xvhaddw.q.d $xr0, $xr0, $xr0
; LA64-NEXT:    xvpermi.d $xr1, $xr0, 2
; LA64-NEXT:    xvadd.d $xr0, $xr1, $xr0
; LA64-NEXT:    xvpickve2gr.d $a0, $xr0, 0
; LA64-NEXT:    st.w $a0, $a1, 0
; LA64-NEXT:    ret
  %v = load <8 x i32>, ptr %src
  %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v)
  store i32 %res, ptr %dst
  ret void
}

define void @vec_reduce_add_v4i64(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v4i64:
; LA32:       # %bb.0:
; LA32-NEXT:    xvld $xr0, $a0, 0
; LA32-NEXT:    xvpermi.q $xr1, $xr0, 1
; LA32-NEXT:    vadd.d $vr0, $vr0, $vr1
; LA32-NEXT:    vpickve2gr.w $a0, $vr0, 3
; LA32-NEXT:    vpickve2gr.w $a2, $vr0, 1
; LA32-NEXT:    add.w $a0, $a2, $a0
; LA32-NEXT:    vpickve2gr.w $a2, $vr0, 2
; LA32-NEXT:    vpickve2gr.w $a3, $vr0, 0
; LA32-NEXT:    add.w $a2, $a3, $a2
; LA32-NEXT:    sltu $a3, $a2, $a3
; LA32-NEXT:    add.w $a0, $a0, $a3
; LA32-NEXT:    st.w $a2, $a1, 0
; LA32-NEXT:    st.w $a0, $a1, 4
; LA32-NEXT:    ret
;
; LA64-LABEL: vec_reduce_add_v4i64:
; LA64:       # %bb.0:
; LA64-NEXT:    xvld $xr0, $a0, 0
; LA64-NEXT:    xvhaddw.q.d $xr0, $xr0, $xr0
; LA64-NEXT:    xvpermi.d $xr1, $xr0, 2
; LA64-NEXT:    xvadd.d $xr0, $xr1, $xr0
; LA64-NEXT:    xvstelm.d $xr0, $a1, 0, 0
; LA64-NEXT:    ret
  %v = load <4 x i64>, ptr %src
  %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)
  store i64 %res, ptr %dst
  ret void
}