; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define <16 x i8> @vrepl_ins_b(i32 %a, i32 %b) {
; CHECK-LABEL: vrepl_ins_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplgr2vr.b $vr0, $a0
; CHECK-NEXT:    vinsgr2vr.b $vr0, $a1, 1
; CHECK-NEXT:    ret
entry:
  %0 = call <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32 %a)
  %1 = call <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8> %0, i32 %b, i32 1)
  ret <16 x i8> %1
}

define <8 x i16> @vrepl_ins_h(i32 %a, i32 %b) {
; CHECK-LABEL: vrepl_ins_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplgr2vr.h $vr0, $a0
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a1, 1
; CHECK-NEXT:    ret
entry:
  %0 = call <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32 %a)
  %1 = call <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16> %0, i32 %b, i32 1)
  ret <8 x i16> %1
}

define <4 x i32> @vrepl_ins_w(i32 %a, i32 %b) {
; CHECK-LABEL: vrepl_ins_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplgr2vr.w $vr0, $a0
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a1, 1
; CHECK-NEXT:    ret
entry:
  %0 = call <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32 %a)
  %1 = call <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32> %0, i32 %b, i32 1)
  ret <4 x i32> %1
}

declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32 immarg)
declare <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32)
declare <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16>, i32, i32 immarg)
declare <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32)
declare <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32>, i32, i32 immarg)
declare <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32)