; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefix=LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefix=LA64

define <4 x float> @insert_bitcast_v4f32(<4 x float> %a, i32 %b) nounwind {
; LA32-LABEL: insert_bitcast_v4f32:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    movgr2fr.w $fa1, $a0
; LA32-NEXT:    vextrins.w $vr0, $vr1, 16
; LA32-NEXT:    ret
;
; LA64-LABEL: insert_bitcast_v4f32:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    vinsgr2vr.w $vr0, $a0, 1
; LA64-NEXT:    ret
entry:
  %c = bitcast i32 %b to float
  %d = insertelement <4 x float> %a, float %c, i32 1
  ret <4 x float> %d
}

define <2 x double> @insert_bitcast_v2f64(<2 x double> %a, i64 %b) nounwind {
; LA32-LABEL: insert_bitcast_v2f64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    movgr2fr.w $fa1, $a0
; LA32-NEXT:    movgr2frh.w $fa1, $a1
; LA32-NEXT:    vextrins.d $vr0, $vr1, 16
; LA32-NEXT:    ret
;
; LA64-LABEL: insert_bitcast_v2f64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    vinsgr2vr.d $vr0, $a0, 1
; LA64-NEXT:    ret
entry:
  %c = bitcast i64 %b to double
  %d = insertelement <2 x double> %a, double %c, i32 1
  ret <2 x double> %d
}