; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64

define <16 x i8> @insert_extract_v16i8(<16 x i8> %a) nounwind {
; CHECK-LABEL: insert_extract_v16i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vextrins.b $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %b = extractelement <16 x i8> %a, i32 15
  %c = insertelement <16 x i8> %a, i8 %b, i32 1
  ret <16 x i8> %c
}

define <8 x i16> @insert_extract_v8i16(<8 x i16> %a) nounwind {
; CHECK-LABEL: insert_extract_v8i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vextrins.h $vr0, $vr0, 23
; CHECK-NEXT:    ret
entry:
  %b = extractelement <8 x i16> %a, i32 7
  %c = insertelement <8 x i16> %a, i16 %b, i32 1
  ret <8 x i16> %c
}

define <4 x i32> @insert_extract_v4i32(<4 x i32> %a) nounwind {
; CHECK-LABEL: insert_extract_v4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vextrins.w $vr0, $vr0, 19
; CHECK-NEXT:    ret
entry:
  %b = extractelement <4 x i32> %a, i32 3
  %c = insertelement <4 x i32> %a, i32 %b, i32 1
  ret <4 x i32> %c
}

define <4 x float> @insert_extract_v4f32(<4 x float> %a) nounwind {
; CHECK-LABEL: insert_extract_v4f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vextrins.w $vr0, $vr0, 3
; CHECK-NEXT:    ret
entry:
  %b = extractelement <4 x float> %a, i32 3
  %c = insertelement <4 x float> %a, float %b, i32 0
  ret <4 x float> %c
}

define <2 x i64> @insert_extract_v2i64(<2 x i64> %a) nounwind {
; LA32-LABEL: insert_extract_v2i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    vori.b $vr1, $vr0, 0
; LA32-NEXT:    vextrins.w $vr1, $vr0, 2
; LA32-NEXT:    vextrins.w $vr1, $vr0, 19
; LA32-NEXT:    vori.b $vr0, $vr1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: insert_extract_v2i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    vextrins.d $vr0, $vr0, 1
; LA64-NEXT:    ret
entry:
  %b = extractelement <2 x i64> %a, i32 1
  %c = insertelement <2 x i64> %a, i64 %b, i32 0
  ret <2 x i64> %c
}

define <2 x double> @insert_extract_v2f64(<2 x double> %a) nounwind {
; CHECK-LABEL: insert_extract_v2f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vextrins.d $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %b = extractelement <2 x double> %a, i32 1
  %c = insertelement <2 x double> %a, double %b, i32 0
  ret <2 x double> %c
}