; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
; RUN:   | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
; RUN:   | FileCheck -check-prefix=RV64F %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
; RUN:   | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
; RUN:   | FileCheck -check-prefix=RV64F %s

;; `.insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is
;; the raw encoding for `fadd.s`

@gf = external global float

define float @constraint_f_modifier_N_float(float %a) nounwind {
; RV32F-LABEL: constraint_f_modifier_N_float:
; RV32F:       # %bb.0:
; RV32F-NEXT:    lui a1, %hi(gf)
; RV32F-NEXT:    flw fa5, %lo(gf)(a1)
; RV32F-NEXT:    fmv.w.x fa4, a0
; RV32F-NEXT:    #APP
; RV32F-NEXT:    .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
; RV32F-NEXT:    #NO_APP
; RV32F-NEXT:    fmv.x.w a0, fa5
; RV32F-NEXT:    ret
;
; RV64F-LABEL: constraint_f_modifier_N_float:
; RV64F:       # %bb.0:
; RV64F-NEXT:    lui a1, %hi(gf)
; RV64F-NEXT:    flw fa5, %lo(gf)(a1)
; RV64F-NEXT:    fmv.w.x fa4, a0
; RV64F-NEXT:    #APP
; RV64F-NEXT:    .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
; RV64F-NEXT:    #NO_APP
; RV64F-NEXT:    fmv.x.w a0, fa5
; RV64F-NEXT:    ret
  %1 = load float, ptr @gf
  %2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=f,f,f"(float %a, float %1)
  ret float %2
}


define float @constraint_cf_modifier_N_float(float %a) nounwind {
; RV32F-LABEL: constraint_cf_modifier_N_float:
; RV32F:       # %bb.0:
; RV32F-NEXT:    lui a1, %hi(gf)
; RV32F-NEXT:    flw fa5, %lo(gf)(a1)
; RV32F-NEXT:    fmv.w.x fa4, a0
; RV32F-NEXT:    #APP
; RV32F-NEXT:    .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
; RV32F-NEXT:    #NO_APP
; RV32F-NEXT:    fmv.x.w a0, fa5
; RV32F-NEXT:    ret
;
; RV64F-LABEL: constraint_cf_modifier_N_float:
; RV64F:       # %bb.0:
; RV64F-NEXT:    lui a1, %hi(gf)
; RV64F-NEXT:    flw fa5, %lo(gf)(a1)
; RV64F-NEXT:    fmv.w.x fa4, a0
; RV64F-NEXT:    #APP
; RV64F-NEXT:    .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
; RV64F-NEXT:    #NO_APP
; RV64F-NEXT:    fmv.x.w a0, fa5
; RV64F-NEXT:    ret
  %1 = load float, ptr @gf
  %2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=^cf,^cf,^cf"(float %a, float %1)
  ret float %2
}

define float @modifier_N_float_abi_name(float %a) nounwind {
; RV32F-LABEL: modifier_N_float_abi_name:
; RV32F:       # %bb.0:
; RV32F-NEXT:    lui a1, %hi(gf)
; RV32F-NEXT:    flw fs0, %lo(gf)(a1)
; RV32F-NEXT:    fmv.w.x fa0, a0
; RV32F-NEXT:    #APP
; RV32F-NEXT:    .insn 0x4, 0x53 | (0 << 7) | (10 << 15) | (8 << 20)
; RV32F-NEXT:    #NO_APP
; RV32F-NEXT:    fmv.x.w a0, ft0
; RV32F-NEXT:    ret
;
; RV64F-LABEL: modifier_N_float_abi_name:
; RV64F:       # %bb.0:
; RV64F-NEXT:    lui a1, %hi(gf)
; RV64F-NEXT:    flw fs0, %lo(gf)(a1)
; RV64F-NEXT:    fmv.w.x fa0, a0
; RV64F-NEXT:    #APP
; RV64F-NEXT:    .insn 0x4, 0x53 | (0 << 7) | (10 << 15) | (8 << 20)
; RV64F-NEXT:    #NO_APP
; RV64F-NEXT:    fmv.x.w a0, ft0
; RV64F-NEXT:    ret
  %1 = load float, ptr @gf
  %2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "={ft0},{fa0},{fs0}"(float %a, float %1)
  ret float %2
}