; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN

define void @fcmp_oeq_vv_v8f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_vv_v8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v9, (a1)
; ZVFH-NEXT:    vmfeq.vv v8, v8, v9
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_vv_v8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a1)
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT:    vsm.v v12, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = load <8 x half>, ptr %y
  %c = fcmp oeq <8 x half> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_oeq_vv_v8f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_vv_v8f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v9, (a1)
; ZVFH-NEXT:    vmfeq.vv v8, v8, v9
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_vv_v8f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a1)
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT:    vsm.v v12, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = load <8 x half>, ptr %y
  %c = fcmp nnan oeq <8 x half> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_une_vv_v4f32(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vv_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v9, (a1)
; CHECK-NEXT:    vmfne.vv v0, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = load <4 x float>, ptr %y
  %c = fcmp une <4 x float> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_une_vv_v4f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vv_v4f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v9, (a1)
; CHECK-NEXT:    vmfne.vv v0, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = load <4 x float>, ptr %y
  %c = fcmp nnan une <4 x float> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ogt_vv_v2f64(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vv_v2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v9, (a1)
; CHECK-NEXT:    vmflt.vv v0, v9, v8
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = load <2 x double>, ptr %y
  %c = fcmp ogt <2 x double> %a, %b
  store <2 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ogt_vv_v2f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v9, (a1)
; CHECK-NEXT:    vmflt.vv v0, v9, v8
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = load <2 x double>, ptr %y
  %c = fcmp nnan ogt <2 x double> %a, %b
  store <2 x i1> %c, ptr %z
  ret void
}

define void @fcmp_olt_vv_v16f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_vv_v16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v10, (a1)
; ZVFH-NEXT:    vmflt.vv v12, v8, v10
; ZVFH-NEXT:    vsm.v v12, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_vv_v16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a1)
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT:    vsm.v v16, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = load <16 x half>, ptr %y
  %c = fcmp olt <16 x half> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_olt_vv_v16f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_vv_v16f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v10, (a1)
; ZVFH-NEXT:    vmflt.vv v12, v8, v10
; ZVFH-NEXT:    vsm.v v12, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_vv_v16f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a1)
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT:    vsm.v v16, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = load <16 x half>, ptr %y
  %c = fcmp nnan olt <16 x half> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_oge_vv_v8f32(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_vv_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v10, (a1)
; CHECK-NEXT:    vmfle.vv v12, v10, v8
; CHECK-NEXT:    vsm.v v12, (a2)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = load <8 x float>, ptr %y
  %c = fcmp oge <8 x float> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_oge_vv_v8f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_vv_v8f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v10, (a1)
; CHECK-NEXT:    vmfle.vv v12, v10, v8
; CHECK-NEXT:    vsm.v v12, (a2)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = load <8 x float>, ptr %y
  %c = fcmp nnan oge <8 x float> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ole_vv_v4f64(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_vv_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v10, (a1)
; CHECK-NEXT:    vmfle.vv v0, v8, v10
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = load <4 x double>, ptr %y
  %c = fcmp ole <4 x double> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ole_vv_v4f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v10, (a1)
; CHECK-NEXT:    vmfle.vv v0, v8, v10
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = load <4 x double>, ptr %y
  %c = fcmp nnan ole <4 x double> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ule_vv_v32f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_vv_v32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a3, 32
; ZVFH-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v12, (a1)
; ZVFH-NEXT:    vmflt.vv v16, v12, v8
; ZVFH-NEXT:    vmnot.m v8, v16
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_vv_v32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a3, 32
; ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    vle16.v v24, (a1)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v24, v16, v8
; ZVFHMIN-NEXT:    vmnot.m v8, v24
; ZVFHMIN-NEXT:    vsm.v v8, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = load <32 x half>, ptr %y
  %c = fcmp ule <32 x half> %a, %b
  store <32 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ule_vv_v32f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_vv_v32f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a3, 32
; ZVFH-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v12, (a1)
; ZVFH-NEXT:    vmfle.vv v16, v8, v12
; ZVFH-NEXT:    vsm.v v16, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_vv_v32f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a3, 32
; ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a1)
; ZVFHMIN-NEXT:    vle16.v v24, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmfle.vv v24, v16, v8
; ZVFHMIN-NEXT:    vsm.v v24, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = load <32 x half>, ptr %y
  %c = fcmp nnan ule <32 x half> %a, %b
  store <32 x i1> %c, ptr %z
  ret void
}

define void @fcmp_uge_vv_v16f32(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_vv_v16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v12, (a1)
; CHECK-NEXT:    vmflt.vv v16, v8, v12
; CHECK-NEXT:    vmnot.m v8, v16
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = load <16 x float>, ptr %y
  %c = fcmp uge <16 x float> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_uge_vv_v16f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_vv_v16f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v12, (a1)
; CHECK-NEXT:    vmfle.vv v16, v12, v8
; CHECK-NEXT:    vsm.v v16, (a2)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = load <16 x float>, ptr %y
  %c = fcmp nnan uge <16 x float> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ult_vv_v8f64(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_vv_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v12, (a1)
; CHECK-NEXT:    vmfle.vv v16, v12, v8
; CHECK-NEXT:    vmnot.m v8, v16
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = load <8 x double>, ptr %y
  %c = fcmp ult <8 x double> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ult_vv_v8f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_vv_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v12, (a1)
; CHECK-NEXT:    vmflt.vv v16, v8, v12
; CHECK-NEXT:    vsm.v v16, (a2)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = load <8 x double>, ptr %y
  %c = fcmp nnan ult <8 x double> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ugt_vv_v64f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_vv_v64f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a3, 64
; ZVFH-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v16, (a1)
; ZVFH-NEXT:    vmfle.vv v24, v8, v16
; ZVFH-NEXT:    vmnot.m v8, v24
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    addi sp, sp, -512
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 512
; RV32ZVFHMIN-NEXT:    sw ra, 508(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    sw s0, 504(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
; RV32ZVFHMIN-NEXT:    addi s0, sp, 512
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
; RV32ZVFHMIN-NEXT:    li a3, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
; RV32ZVFHMIN-NEXT:    vle16.v v16, (a1)
; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
; RV32ZVFHMIN-NEXT:    addi a1, sp, 256
; RV32ZVFHMIN-NEXT:    vse16.v v16, (a0)
; RV32ZVFHMIN-NEXT:    vse16.v v8, (a1)
; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 320(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 318(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 316(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 314(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 312(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 310(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 308(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 306(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 176(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 304(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a0, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
; RV32ZVFHMIN-NEXT:    sb a1, 88(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 174(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 302(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a1, v8
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v16, 7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 87(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 172(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 300(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 7
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 6
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 86(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 170(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 298(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 6
; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 85(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 168(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 296(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v19, v8, 5
; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 84(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 166(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 294(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v21, v8, 4
; RV32ZVFHMIN-NEXT:    vslidedown.vi v23, v16, 3
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 83(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 164(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 292(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 3
; RV32ZVFHMIN-NEXT:    vslidedown.vi v25, v16, 2
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 82(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 162(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 290(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v24, v8, 2
; RV32ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    xori a0, a4, 1
; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 288(sp)
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a4, 64(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 354(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v27, v8, 1
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v16, 15
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 224(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 352(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a1, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a0, v13
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 112(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 222(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 350(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 15
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 111(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 220(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 348(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v15
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 14
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 110(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 218(sp)
; RV32ZVFHMIN-NEXT:    lh t1, 346(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v18
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v19
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
; RV32ZVFHMIN-NEXT:    sb t0, 109(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 216(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 13
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v20
; RV32ZVFHMIN-NEXT:    lh t2, 344(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v21
; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 12
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t2
; RV32ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV32ZVFHMIN-NEXT:    xori a1, t2, 1
; RV32ZVFHMIN-NEXT:    sb a1, 108(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 214(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a0
; RV32ZVFHMIN-NEXT:    lh t3, 342(sp)
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v23
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
; RV32ZVFHMIN-NEXT:    sb a1, 107(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 212(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    lh a7, 340(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s t3, v22
; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v16, 11
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
; RV32ZVFHMIN-NEXT:    sb a5, 106(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 210(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV32ZVFHMIN-NEXT:    lh a6, 338(sp)
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v25
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
; RV32ZVFHMIN-NEXT:    sb a5, 105(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 208(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
; RV32ZVFHMIN-NEXT:    lh t0, 336(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v24
; RV32ZVFHMIN-NEXT:    vslidedown.vi v24, v16, 10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
; RV32ZVFHMIN-NEXT:    sb t0, 104(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 206(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV32ZVFHMIN-NEXT:    lh t1, 334(sp)
; RV32ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v26
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    xori a7, t1, 1
; RV32ZVFHMIN-NEXT:    sb a7, 103(sp)
; RV32ZVFHMIN-NEXT:    lh a7, 204(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    fle.h a6, fa4, fa5
; RV32ZVFHMIN-NEXT:    lh t1, 332(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v27
; RV32ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 9
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    xori a7, t1, 1
; RV32ZVFHMIN-NEXT:    sb a7, 102(sp)
; RV32ZVFHMIN-NEXT:    lh a7, 202(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 330(sp)
; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
; RV32ZVFHMIN-NEXT:    sb a7, 101(sp)
; RV32ZVFHMIN-NEXT:    lh a7, 200(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 328(sp)
; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
; RV32ZVFHMIN-NEXT:    sb a7, 100(sp)
; RV32ZVFHMIN-NEXT:    lh a7, 198(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 326(sp)
; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
; RV32ZVFHMIN-NEXT:    xori t2, t2, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
; RV32ZVFHMIN-NEXT:    sb a7, 99(sp)
; RV32ZVFHMIN-NEXT:    lh a7, 196(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 324(sp)
; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
; RV32ZVFHMIN-NEXT:    xori t1, t1, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
; RV32ZVFHMIN-NEXT:    sb a7, 98(sp)
; RV32ZVFHMIN-NEXT:    lh a7, 194(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 322(sp)
; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 66(sp)
; RV32ZVFHMIN-NEXT:    sb t2, 67(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 68(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
; RV32ZVFHMIN-NEXT:    sb a4, 69(sp)
; RV32ZVFHMIN-NEXT:    sb a1, 70(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 71(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 97(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 382(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v16, 8
; RV32ZVFHMIN-NEXT:    vslidedown.vi v2, v8, 14
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 380(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v0, v8, 13
; RV32ZVFHMIN-NEXT:    vslidedown.vi v4, v8, 12
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 378(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v6, v8, 11
; RV32ZVFHMIN-NEXT:    vslidedown.vi v30, v8, 10
; RV32ZVFHMIN-NEXT:    vslidedown.vi v28, v8, 9
; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 376(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v14
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 374(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v2
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v18
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v0
; RV32ZVFHMIN-NEXT:    lh a1, 372(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v20
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    vmv.x.s t3, v4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 242(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    lh a4, 370(sp)
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v22
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
; RV32ZVFHMIN-NEXT:    sb a1, 121(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 240(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    lh a6, 368(sp)
; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v6
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    sb a4, 120(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 238(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    lh t0, 366(sp)
; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v24
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
; RV32ZVFHMIN-NEXT:    sb t0, 119(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 236(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV32ZVFHMIN-NEXT:    lh t1, 364(sp)
; RV32ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v30
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    xori a5, t1, 1
; RV32ZVFHMIN-NEXT:    sb a5, 118(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 234(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    lh a7, 362(sp)
; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v26
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    xori a6, a7, 1
; RV32ZVFHMIN-NEXT:    sb a6, 117(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 232(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    lh a7, 360(sp)
; RV32ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v28
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    xori a5, a7, 1
; RV32ZVFHMIN-NEXT:    sb a5, 116(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 230(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    lh a6, 358(sp)
; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    fle.h a6, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    xori a5, t2, 1
; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
; RV32ZVFHMIN-NEXT:    sb a6, 115(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 228(sp)
; RV32ZVFHMIN-NEXT:    lh t2, 356(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 76(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 77(sp)
; RV32ZVFHMIN-NEXT:    sb a1, 78(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 79(sp)
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a1, t1, 1
; RV32ZVFHMIN-NEXT:    xori a4, t0, 1
; RV32ZVFHMIN-NEXT:    xori a5, a7, 1
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 72(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 73(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 74(sp)
; RV32ZVFHMIN-NEXT:    sb a1, 75(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t2
; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV32ZVFHMIN-NEXT:    vsm.v v12, (a2)
; RV32ZVFHMIN-NEXT:    addi sp, s0, -512
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 512
; RV32ZVFHMIN-NEXT:    lw ra, 508(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    lw s0, 504(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    .cfi_restore ra
; RV32ZVFHMIN-NEXT:    .cfi_restore s0
; RV32ZVFHMIN-NEXT:    addi sp, sp, 512
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    addi sp, sp, -512
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 512
; RV64ZVFHMIN-NEXT:    sd ra, 504(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    sd s0, 496(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
; RV64ZVFHMIN-NEXT:    addi s0, sp, 512
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
; RV64ZVFHMIN-NEXT:    li a3, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
; RV64ZVFHMIN-NEXT:    vle16.v v16, (a1)
; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
; RV64ZVFHMIN-NEXT:    addi a1, sp, 256
; RV64ZVFHMIN-NEXT:    vse16.v v16, (a0)
; RV64ZVFHMIN-NEXT:    vse16.v v8, (a1)
; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 320(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 318(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 316(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 314(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 312(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 310(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 308(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 306(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 176(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 304(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a0, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
; RV64ZVFHMIN-NEXT:    sb a1, 88(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 174(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 302(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a1, v8
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v16, 7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 87(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 172(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 300(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 7
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 6
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 86(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 170(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 298(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 6
; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 85(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 168(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 296(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v19, v8, 5
; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 84(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 166(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 294(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v21, v8, 4
; RV64ZVFHMIN-NEXT:    vslidedown.vi v23, v16, 3
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 83(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 164(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 292(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 3
; RV64ZVFHMIN-NEXT:    vslidedown.vi v25, v16, 2
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 82(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 162(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 290(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v24, v8, 2
; RV64ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    xori a0, a4, 1
; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 288(sp)
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a4, 64(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 354(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v27, v8, 1
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v16, 15
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 224(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 352(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a1, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a0, v13
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 112(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 222(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 350(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 15
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 111(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 220(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 348(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v15
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 14
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 110(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 218(sp)
; RV64ZVFHMIN-NEXT:    lh t1, 346(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v18
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v19
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
; RV64ZVFHMIN-NEXT:    sb t0, 109(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 216(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 13
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v20
; RV64ZVFHMIN-NEXT:    lh t2, 344(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v21
; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 12
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t2
; RV64ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV64ZVFHMIN-NEXT:    xori a1, t2, 1
; RV64ZVFHMIN-NEXT:    sb a1, 108(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 214(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a0
; RV64ZVFHMIN-NEXT:    lh t3, 342(sp)
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v23
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
; RV64ZVFHMIN-NEXT:    sb a1, 107(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 212(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    lh a7, 340(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s t3, v22
; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v16, 11
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
; RV64ZVFHMIN-NEXT:    sb a5, 106(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 210(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV64ZVFHMIN-NEXT:    lh a6, 338(sp)
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v25
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
; RV64ZVFHMIN-NEXT:    sb a5, 105(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 208(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
; RV64ZVFHMIN-NEXT:    lh t0, 336(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v24
; RV64ZVFHMIN-NEXT:    vslidedown.vi v24, v16, 10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
; RV64ZVFHMIN-NEXT:    sb t0, 104(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 206(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV64ZVFHMIN-NEXT:    lh t1, 334(sp)
; RV64ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v26
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    xori a7, t1, 1
; RV64ZVFHMIN-NEXT:    sb a7, 103(sp)
; RV64ZVFHMIN-NEXT:    lh a7, 204(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    fle.h a6, fa4, fa5
; RV64ZVFHMIN-NEXT:    lh t1, 332(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v27
; RV64ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 9
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    xori a7, t1, 1
; RV64ZVFHMIN-NEXT:    sb a7, 102(sp)
; RV64ZVFHMIN-NEXT:    lh a7, 202(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 330(sp)
; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
; RV64ZVFHMIN-NEXT:    sb a7, 101(sp)
; RV64ZVFHMIN-NEXT:    lh a7, 200(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 328(sp)
; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
; RV64ZVFHMIN-NEXT:    sb a7, 100(sp)
; RV64ZVFHMIN-NEXT:    lh a7, 198(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 326(sp)
; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
; RV64ZVFHMIN-NEXT:    xori t2, t2, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
; RV64ZVFHMIN-NEXT:    sb a7, 99(sp)
; RV64ZVFHMIN-NEXT:    lh a7, 196(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 324(sp)
; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
; RV64ZVFHMIN-NEXT:    xori t1, t1, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
; RV64ZVFHMIN-NEXT:    sb a7, 98(sp)
; RV64ZVFHMIN-NEXT:    lh a7, 194(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 322(sp)
; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 66(sp)
; RV64ZVFHMIN-NEXT:    sb t2, 67(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 68(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
; RV64ZVFHMIN-NEXT:    sb a4, 69(sp)
; RV64ZVFHMIN-NEXT:    sb a1, 70(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 71(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 97(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 382(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v16, 8
; RV64ZVFHMIN-NEXT:    vslidedown.vi v2, v8, 14
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 380(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v0, v8, 13
; RV64ZVFHMIN-NEXT:    vslidedown.vi v4, v8, 12
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 378(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v6, v8, 11
; RV64ZVFHMIN-NEXT:    vslidedown.vi v30, v8, 10
; RV64ZVFHMIN-NEXT:    vslidedown.vi v28, v8, 9
; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 376(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v14
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 374(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v2
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v18
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v0
; RV64ZVFHMIN-NEXT:    lh a1, 372(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v20
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    vmv.x.s t3, v4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 242(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    lh a4, 370(sp)
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v22
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
; RV64ZVFHMIN-NEXT:    sb a1, 121(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 240(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    lh a6, 368(sp)
; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v6
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    sb a4, 120(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 238(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    lh t0, 366(sp)
; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v24
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
; RV64ZVFHMIN-NEXT:    sb t0, 119(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 236(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV64ZVFHMIN-NEXT:    lh t1, 364(sp)
; RV64ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v30
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    xori a5, t1, 1
; RV64ZVFHMIN-NEXT:    sb a5, 118(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 234(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    lh a7, 362(sp)
; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v26
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    xori a6, a7, 1
; RV64ZVFHMIN-NEXT:    sb a6, 117(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 232(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    lh a7, 360(sp)
; RV64ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v28
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    xori a5, a7, 1
; RV64ZVFHMIN-NEXT:    sb a5, 116(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 230(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    lh a6, 358(sp)
; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    fle.h a6, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    xori a5, t2, 1
; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
; RV64ZVFHMIN-NEXT:    sb a6, 115(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 228(sp)
; RV64ZVFHMIN-NEXT:    lh t2, 356(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 76(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 77(sp)
; RV64ZVFHMIN-NEXT:    sb a1, 78(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 79(sp)
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a1, t1, 1
; RV64ZVFHMIN-NEXT:    xori a4, t0, 1
; RV64ZVFHMIN-NEXT:    xori a5, a7, 1
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 72(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 73(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 74(sp)
; RV64ZVFHMIN-NEXT:    sb a1, 75(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t2
; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV64ZVFHMIN-NEXT:    vsm.v v12, (a2)
; RV64ZVFHMIN-NEXT:    addi sp, s0, -512
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 512
; RV64ZVFHMIN-NEXT:    ld ra, 504(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    ld s0, 496(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    .cfi_restore ra
; RV64ZVFHMIN-NEXT:    .cfi_restore s0
; RV64ZVFHMIN-NEXT:    addi sp, sp, 512
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV64ZVFHMIN-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = load <64 x half>, ptr %y
  %c = fcmp ugt <64 x half> %a, %b
  store <64 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ugt_vv_v64f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_vv_v64f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a3, 64
; ZVFH-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v16, (a1)
; ZVFH-NEXT:    vmflt.vv v24, v16, v8
; ZVFH-NEXT:    vsm.v v24, (a2)
; ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16_nonans:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    addi sp, sp, -512
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 512
; RV32ZVFHMIN-NEXT:    sw ra, 508(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    sw s0, 504(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
; RV32ZVFHMIN-NEXT:    addi s0, sp, 512
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
; RV32ZVFHMIN-NEXT:    li a3, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
; RV32ZVFHMIN-NEXT:    vle16.v v16, (a0)
; RV32ZVFHMIN-NEXT:    vle16.v v8, (a1)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 256
; RV32ZVFHMIN-NEXT:    addi a1, sp, 128
; RV32ZVFHMIN-NEXT:    vse16.v v16, (a0)
; RV32ZVFHMIN-NEXT:    vse16.v v8, (a1)
; RV32ZVFHMIN-NEXT:    lh a0, 320(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 192(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 318(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 190(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 316(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 188(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 314(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 186(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 312(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 184(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 310(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 182(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 308(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 180(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 306(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 178(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 304(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 176(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 302(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 174(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 300(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 172(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 298(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 170(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a0, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a1, 85(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 296(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 168(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a1, v8
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v16, 7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a4, 84(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 294(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 166(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 7
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 6
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a4, 83(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 292(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 164(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 6
; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a4, 82(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 290(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 162(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v19, v8, 5
; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    sb a4, 81(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 288(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 160(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a1, 64(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 354(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 226(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v21, v8, 4
; RV32ZVFHMIN-NEXT:    vslidedown.vi v23, v16, 3
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 352(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 224(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 3
; RV32ZVFHMIN-NEXT:    vslidedown.vi v25, v16, 2
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 350(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 222(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v24, v8, 2
; RV32ZVFHMIN-NEXT:    vslidedown.vi v27, v16, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 348(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 220(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v26, v8, 1
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v16, 15
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 346(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 218(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a1, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a0, v13
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a4, 109(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 344(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 216(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 15
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a4, 108(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 342(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 214(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v15
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 14
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a4, 107(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 340(sp)
; RV32ZVFHMIN-NEXT:    lh t1, 212(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v18
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v19
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb t0, 106(sp)
; RV32ZVFHMIN-NEXT:    lh t1, 338(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 13
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV32ZVFHMIN-NEXT:    lh t2, 210(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v21
; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 12
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t2
; RV32ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV32ZVFHMIN-NEXT:    sb t2, 105(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 336(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a0
; RV32ZVFHMIN-NEXT:    lh t3, 208(sp)
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v23
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    sb a1, 104(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 334(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    lh a7, 206(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s t3, v22
; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v16, 11
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    sb a5, 103(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 332(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV32ZVFHMIN-NEXT:    lh a6, 204(sp)
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v25
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    sb a5, 102(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 330(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
; RV32ZVFHMIN-NEXT:    lh t0, 202(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v24
; RV32ZVFHMIN-NEXT:    vslidedown.vi v24, v16, 10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV32ZVFHMIN-NEXT:    sb t0, 101(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 328(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV32ZVFHMIN-NEXT:    lh t1, 200(sp)
; RV32ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v27
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    sb t1, 100(sp)
; RV32ZVFHMIN-NEXT:    lh a7, 326(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
; RV32ZVFHMIN-NEXT:    lh t1, 198(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v26
; RV32ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 9
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    sb t1, 99(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 324(sp)
; RV32ZVFHMIN-NEXT:    lh t1, 196(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb t0, 98(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 322(sp)
; RV32ZVFHMIN-NEXT:    lh t1, 194(sp)
; RV32ZVFHMIN-NEXT:    sb a7, 65(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 66(sp)
; RV32ZVFHMIN-NEXT:    sb t2, 67(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 68(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a4, 69(sp)
; RV32ZVFHMIN-NEXT:    sb a1, 70(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 71(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 97(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 382(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 254(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v16, 8
; RV32ZVFHMIN-NEXT:    vslidedown.vi v2, v8, 14
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 380(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 252(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v0, v8, 13
; RV32ZVFHMIN-NEXT:    vslidedown.vi v4, v8, 12
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 378(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 250(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v6, v8, 11
; RV32ZVFHMIN-NEXT:    vslidedown.vi v30, v8, 10
; RV32ZVFHMIN-NEXT:    vslidedown.vi v28, v8, 9
; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 376(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 248(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v14
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 374(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 246(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v2
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v18
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 372(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v0
; RV32ZVFHMIN-NEXT:    lh a1, 244(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v20
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    vmv.x.s t3, v4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV32ZVFHMIN-NEXT:    lh a1, 370(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    lh a4, 242(sp)
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v22
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    sb a1, 121(sp)
; RV32ZVFHMIN-NEXT:    lh a4, 368(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    lh a6, 240(sp)
; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v6
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    sb a4, 120(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 366(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    lh t0, 238(sp)
; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v24
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV32ZVFHMIN-NEXT:    sb t0, 119(sp)
; RV32ZVFHMIN-NEXT:    lh t0, 364(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV32ZVFHMIN-NEXT:    lh t1, 236(sp)
; RV32ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v30
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV32ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    sb t1, 118(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 362(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    lh a7, 234(sp)
; RV32ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v26
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    sb a7, 117(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 360(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV32ZVFHMIN-NEXT:    lh a7, 232(sp)
; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v28
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV32ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    sb a7, 116(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 358(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    lh a6, 230(sp)
; RV32ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV32ZVFHMIN-NEXT:    sb a6, 115(sp)
; RV32ZVFHMIN-NEXT:    lh a5, 356(sp)
; RV32ZVFHMIN-NEXT:    lh a6, 228(sp)
; RV32ZVFHMIN-NEXT:    sb t2, 76(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 77(sp)
; RV32ZVFHMIN-NEXT:    sb a1, 78(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 79(sp)
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 72(sp)
; RV32ZVFHMIN-NEXT:    sb a7, 73(sp)
; RV32ZVFHMIN-NEXT:    sb t0, 74(sp)
; RV32ZVFHMIN-NEXT:    sb t1, 75(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV32ZVFHMIN-NEXT:    vsm.v v12, (a2)
; RV32ZVFHMIN-NEXT:    addi sp, s0, -512
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 512
; RV32ZVFHMIN-NEXT:    lw ra, 508(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    lw s0, 504(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    .cfi_restore ra
; RV32ZVFHMIN-NEXT:    .cfi_restore s0
; RV32ZVFHMIN-NEXT:    addi sp, sp, 512
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16_nonans:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    addi sp, sp, -512
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 512
; RV64ZVFHMIN-NEXT:    sd ra, 504(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    sd s0, 496(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
; RV64ZVFHMIN-NEXT:    addi s0, sp, 512
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
; RV64ZVFHMIN-NEXT:    li a3, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
; RV64ZVFHMIN-NEXT:    vle16.v v16, (a0)
; RV64ZVFHMIN-NEXT:    vle16.v v8, (a1)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 256
; RV64ZVFHMIN-NEXT:    addi a1, sp, 128
; RV64ZVFHMIN-NEXT:    vse16.v v16, (a0)
; RV64ZVFHMIN-NEXT:    vse16.v v8, (a1)
; RV64ZVFHMIN-NEXT:    lh a0, 320(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 192(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 318(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 190(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 316(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 188(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 314(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 186(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 312(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 184(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 310(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 182(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 308(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 180(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 306(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 178(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 304(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 176(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 302(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 174(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 300(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 172(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 298(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 170(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a0, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a1, 85(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 296(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 168(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a1, v8
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v16, 7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a4, 84(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 294(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 166(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 7
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 6
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a4, 83(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 292(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 164(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 6
; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a4, 82(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 290(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 162(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v19, v8, 5
; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    sb a4, 81(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 288(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 160(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a1, 64(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 354(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 226(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v21, v8, 4
; RV64ZVFHMIN-NEXT:    vslidedown.vi v23, v16, 3
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 352(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 224(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 3
; RV64ZVFHMIN-NEXT:    vslidedown.vi v25, v16, 2
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 350(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 222(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v24, v8, 2
; RV64ZVFHMIN-NEXT:    vslidedown.vi v27, v16, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 348(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 220(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v26, v8, 1
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v16, 15
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 346(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 218(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a1, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a0, v13
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a4, 109(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 344(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 216(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 15
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a4, 108(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 342(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 214(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v15
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 14
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a4, 107(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 340(sp)
; RV64ZVFHMIN-NEXT:    lh t1, 212(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v18
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v19
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb t0, 106(sp)
; RV64ZVFHMIN-NEXT:    lh t1, 338(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 13
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV64ZVFHMIN-NEXT:    lh t2, 210(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v21
; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 12
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t2
; RV64ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV64ZVFHMIN-NEXT:    sb t2, 105(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 336(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a0
; RV64ZVFHMIN-NEXT:    lh t3, 208(sp)
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v23
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    sb a1, 104(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 334(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    lh a7, 206(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s t3, v22
; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v16, 11
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    sb a5, 103(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 332(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV64ZVFHMIN-NEXT:    lh a6, 204(sp)
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v25
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    sb a5, 102(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 330(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
; RV64ZVFHMIN-NEXT:    lh t0, 202(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v24
; RV64ZVFHMIN-NEXT:    vslidedown.vi v24, v16, 10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV64ZVFHMIN-NEXT:    sb t0, 101(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 328(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV64ZVFHMIN-NEXT:    lh t1, 200(sp)
; RV64ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v27
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    sb t1, 100(sp)
; RV64ZVFHMIN-NEXT:    lh a7, 326(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
; RV64ZVFHMIN-NEXT:    lh t1, 198(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v26
; RV64ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 9
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    sb t1, 99(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 324(sp)
; RV64ZVFHMIN-NEXT:    lh t1, 196(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb t0, 98(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 322(sp)
; RV64ZVFHMIN-NEXT:    lh t1, 194(sp)
; RV64ZVFHMIN-NEXT:    sb a7, 65(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 66(sp)
; RV64ZVFHMIN-NEXT:    sb t2, 67(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 68(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a4, 69(sp)
; RV64ZVFHMIN-NEXT:    sb a1, 70(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 71(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 97(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 382(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 254(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v16, 8
; RV64ZVFHMIN-NEXT:    vslidedown.vi v2, v8, 14
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 380(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 252(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v0, v8, 13
; RV64ZVFHMIN-NEXT:    vslidedown.vi v4, v8, 12
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 378(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 250(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v6, v8, 11
; RV64ZVFHMIN-NEXT:    vslidedown.vi v30, v8, 10
; RV64ZVFHMIN-NEXT:    vslidedown.vi v28, v8, 9
; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 376(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 248(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v14
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 374(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 246(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v2
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v18
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 372(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v0
; RV64ZVFHMIN-NEXT:    lh a1, 244(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v20
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    vmv.x.s t3, v4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV64ZVFHMIN-NEXT:    lh a1, 370(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    lh a4, 242(sp)
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v22
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    sb a1, 121(sp)
; RV64ZVFHMIN-NEXT:    lh a4, 368(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    lh a6, 240(sp)
; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v6
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    sb a4, 120(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 366(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    lh t0, 238(sp)
; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v24
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV64ZVFHMIN-NEXT:    sb t0, 119(sp)
; RV64ZVFHMIN-NEXT:    lh t0, 364(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
; RV64ZVFHMIN-NEXT:    lh t1, 236(sp)
; RV64ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v30
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
; RV64ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    sb t1, 118(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 362(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    lh a7, 234(sp)
; RV64ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v26
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    sb a7, 117(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 360(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
; RV64ZVFHMIN-NEXT:    lh a7, 232(sp)
; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v28
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
; RV64ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    sb a7, 116(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 358(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    lh a6, 230(sp)
; RV64ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
; RV64ZVFHMIN-NEXT:    sb a6, 115(sp)
; RV64ZVFHMIN-NEXT:    lh a5, 356(sp)
; RV64ZVFHMIN-NEXT:    lh a6, 228(sp)
; RV64ZVFHMIN-NEXT:    sb t2, 76(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 77(sp)
; RV64ZVFHMIN-NEXT:    sb a1, 78(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 79(sp)
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 72(sp)
; RV64ZVFHMIN-NEXT:    sb a7, 73(sp)
; RV64ZVFHMIN-NEXT:    sb t0, 74(sp)
; RV64ZVFHMIN-NEXT:    sb t1, 75(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV64ZVFHMIN-NEXT:    vsm.v v12, (a2)
; RV64ZVFHMIN-NEXT:    addi sp, s0, -512
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 512
; RV64ZVFHMIN-NEXT:    ld ra, 504(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    ld s0, 496(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    .cfi_restore ra
; RV64ZVFHMIN-NEXT:    .cfi_restore s0
; RV64ZVFHMIN-NEXT:    addi sp, sp, 512
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV64ZVFHMIN-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = load <64 x half>, ptr %y
  %c = fcmp nnan ugt <64 x half> %a, %b
  store <64 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ueq_vv_v32f32(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_vv_v32f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a3, 32
; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v16, (a1)
; CHECK-NEXT:    vmflt.vv v24, v8, v16
; CHECK-NEXT:    vmflt.vv v25, v16, v8
; CHECK-NEXT:    vmnor.mm v8, v25, v24
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = load <32 x float>, ptr %y
  %c = fcmp ueq <32 x float> %a, %b
  store <32 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ueq_vv_v32f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_vv_v32f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a3, 32
; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v16, (a1)
; CHECK-NEXT:    vmfeq.vv v24, v8, v16
; CHECK-NEXT:    vsm.v v24, (a2)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = load <32 x float>, ptr %y
  %c = fcmp nnan ueq <32 x float> %a, %b
  store <32 x i1> %c, ptr %z
  ret void
}

define void @fcmp_one_vv_v8f64(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_one_vv_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v16, (a1)
; CHECK-NEXT:    vmflt.vv v24, v8, v16
; CHECK-NEXT:    vmflt.vv v25, v16, v8
; CHECK-NEXT:    vmor.mm v8, v25, v24
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = load <16 x double>, ptr %y
  %c = fcmp one <16 x double> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_one_vv_v8f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_one_vv_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v16, (a1)
; CHECK-NEXT:    vmfne.vv v24, v8, v16
; CHECK-NEXT:    vsm.v v24, (a2)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = load <16 x double>, ptr %y
  %c = fcmp nnan one <16 x double> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ord_vv_v4f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ord_vv_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a1)
; ZVFH-NEXT:    vle16.v v9, (a0)
; ZVFH-NEXT:    vmfeq.vv v8, v8, v8
; ZVFH-NEXT:    vmfeq.vv v9, v9, v9
; ZVFH-NEXT:    vmand.mm v0, v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ord_vv_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a1)
; ZVFHMIN-NEXT:    vle16.v v9, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v9, v10, v10
; ZVFHMIN-NEXT:    vmfeq.vv v8, v8, v8
; ZVFHMIN-NEXT:    vmand.mm v0, v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <4 x half>, ptr %x
  %b = load <4 x half>, ptr %y
  %c = fcmp ord <4 x half> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_uno_vv_v4f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_uno_vv_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a1)
; ZVFH-NEXT:    vle16.v v9, (a0)
; ZVFH-NEXT:    vmfne.vv v8, v8, v8
; ZVFH-NEXT:    vmfne.vv v9, v9, v9
; ZVFH-NEXT:    vmor.mm v0, v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_uno_vv_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a1)
; ZVFHMIN-NEXT:    vle16.v v9, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v9, v10, v10
; ZVFHMIN-NEXT:    vmfne.vv v8, v8, v8
; ZVFHMIN-NEXT:    vmor.mm v0, v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <2 x half>, ptr %x
  %b = load <2 x half>, ptr %y
  %c = fcmp uno <2 x half> %a, %b
  store <2 x i1> %c, ptr %z
  ret void
}

define void @fcmp_oeq_vf_v8f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_vf_v8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfeq.vf v8, v8, fa0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_vf_v8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v12, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v8, v10
; ZVFHMIN-NEXT:    vsm.v v12, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = insertelement <8 x half> poison, half %y, i32 0
  %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
  %d = fcmp oeq <8 x half> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oeq_vf_v8f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_vf_v8f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfeq.vf v8, v8, fa0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_vf_v8f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v12, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v8, v10
; ZVFHMIN-NEXT:    vsm.v v12, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = insertelement <8 x half> poison, half %y, i32 0
  %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan oeq <8 x half> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_une_vf_v4f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = insertelement <4 x float> poison, float %y, i32 0
  %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
  %d = fcmp une <4 x float> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_une_vf_v4f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = insertelement <4 x float> poison, float %y, i32 0
  %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
  %d = fcmp nnan une <4 x float> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ogt_vf_v2f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = insertelement <2 x double> poison, double %y, i32 0
  %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
  %d = fcmp ogt <2 x double> %a, %c
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ogt_vf_v2f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = insertelement <2 x double> poison, double %y, i32 0
  %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
  %d = fcmp nnan ogt <2 x double> %a, %c
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_olt_vf_v16f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_vf_v16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmflt.vf v10, v8, fa0
; ZVFH-NEXT:    vsm.v v10, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_vf_v16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v16, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v8, v12
; ZVFHMIN-NEXT:    vsm.v v16, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = insertelement <16 x half> poison, half %y, i32 0
  %c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
  %d = fcmp olt <16 x half> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_olt_vf_v16f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_vf_v16f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmflt.vf v10, v8, fa0
; ZVFH-NEXT:    vsm.v v10, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_vf_v16f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v16, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v8, v12
; ZVFHMIN-NEXT:    vsm.v v16, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = insertelement <16 x half> poison, half %y, i32 0
  %c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan olt <16 x half> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oge_vf_v8f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_vf_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v10, v8, fa0
; CHECK-NEXT:    vsm.v v10, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = insertelement <8 x float> poison, float %y, i32 0
  %c = shufflevector <8 x float> %b, <8 x float> poison, <8 x i32> zeroinitializer
  %d = fcmp oge <8 x float> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oge_vf_v8f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_vf_v8f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v10, v8, fa0
; CHECK-NEXT:    vsm.v v10, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = insertelement <8 x float> poison, float %y, i32 0
  %c = shufflevector <8 x float> %b, <8 x float> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan oge <8 x float> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ole_vf_v4f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_vf_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = insertelement <4 x double> poison, double %y, i32 0
  %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
  %d = fcmp ole <4 x double> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ole_vf_v4f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = insertelement <4 x double> poison, double %y, i32 0
  %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
  %d = fcmp nnan ole <4 x double> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ule_vf_v32f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_vf_v32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 32
; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfgt.vf v12, v8, fa0
; ZVFH-NEXT:    vmnot.m v8, v12
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_vf_v32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a2, 32
; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v24, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v24, v16, v8
; ZVFHMIN-NEXT:    vmnot.m v8, v24
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = insertelement <32 x half> poison, half %y, i32 0
  %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
  %d = fcmp ule <32 x half> %a, %c
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ule_vf_v32f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_vf_v32f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 32
; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfle.vf v12, v8, fa0
; ZVFH-NEXT:    vsm.v v12, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_vf_v32f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a2, 32
; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v24, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmfle.vv v24, v8, v16
; ZVFHMIN-NEXT:    vsm.v v24, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = insertelement <32 x half> poison, half %y, i32 0
  %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
  %d = fcmp nnan ule <32 x half> %a, %c
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uge_vf_v16f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_vf_v16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v12, v8, fa0
; CHECK-NEXT:    vmnot.m v8, v12
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = insertelement <16 x float> poison, float %y, i32 0
  %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
  %d = fcmp uge <16 x float> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uge_vf_v16f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_vf_v16f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v12, v8, fa0
; CHECK-NEXT:    vsm.v v12, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = insertelement <16 x float> poison, float %y, i32 0
  %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan uge <16 x float> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ult_vf_v8f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_vf_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v12, v8, fa0
; CHECK-NEXT:    vmnot.m v8, v12
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = insertelement <8 x double> poison, double %y, i32 0
  %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
  %d = fcmp ult <8 x double> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ult_vf_v8f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_vf_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v12, v8, fa0
; CHECK-NEXT:    vsm.v v12, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = insertelement <8 x double> poison, double %y, i32 0
  %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan ult <8 x double> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ugt_vf_v64f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_vf_v64f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 64
; ZVFH-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfle.vf v16, v8, fa0
; ZVFH-NEXT:    vmnot.m v8, v16
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    addi sp, sp, -384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
; RV32ZVFHMIN-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
; RV32ZVFHMIN-NEXT:    addi s0, sp, 384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
; RV32ZVFHMIN-NEXT:    li a2, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
; RV32ZVFHMIN-NEXT:    vse16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 176(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 174(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 172(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 170(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 85(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 168(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 84(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 166(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 83(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 164(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 82(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 162(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a3, 64(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 224(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 222(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 220(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 218(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 109(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 216(sp)
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
; RV32ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 108(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 214(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 107(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 212(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 106(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 210(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v11
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v13
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 105(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 208(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v14
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v15
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 104(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 206(sp)
; RV32ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fle.h a4, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 103(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 204(sp)
; RV32ZVFHMIN-NEXT:    fle.h a5, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    fle.h a6, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 102(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 202(sp)
; RV32ZVFHMIN-NEXT:    fle.h a7, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    fle.h t0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 101(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 200(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    fle.h t1, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 100(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 198(sp)
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 99(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 196(sp)
; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
; RV32ZVFHMIN-NEXT:    xori t1, t1, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 98(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 194(sp)
; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV32ZVFHMIN-NEXT:    sb t0, 66(sp)
; RV32ZVFHMIN-NEXT:    sb a7, 67(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 68(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a5, 69(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 70(sp)
; RV32ZVFHMIN-NEXT:    sb a3, 71(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 97(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 242(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 121(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 240(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 120(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 238(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v18
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v22
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 119(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 236(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 118(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 234(sp)
; RV32ZVFHMIN-NEXT:    fle.h a4, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    fle.h a5, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 117(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 232(sp)
; RV32ZVFHMIN-NEXT:    fle.h a6, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    fle.h a7, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 116(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 230(sp)
; RV32ZVFHMIN-NEXT:    fle.h t0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    fle.h t1, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 115(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 228(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 76(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 77(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 78(sp)
; RV32ZVFHMIN-NEXT:    sb a3, 79(sp)
; RV32ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a4, a7, 1
; RV32ZVFHMIN-NEXT:    xori a5, t0, 1
; RV32ZVFHMIN-NEXT:    xori a6, t1, 1
; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
; RV32ZVFHMIN-NEXT:    sb a3, 72(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 73(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 74(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 75(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV32ZVFHMIN-NEXT:    vsm.v v12, (a1)
; RV32ZVFHMIN-NEXT:    addi sp, s0, -384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
; RV32ZVFHMIN-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    .cfi_restore ra
; RV32ZVFHMIN-NEXT:    .cfi_restore s0
; RV32ZVFHMIN-NEXT:    addi sp, sp, 384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    addi sp, sp, -384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
; RV64ZVFHMIN-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
; RV64ZVFHMIN-NEXT:    addi s0, sp, 384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
; RV64ZVFHMIN-NEXT:    li a2, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
; RV64ZVFHMIN-NEXT:    vse16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 176(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 174(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 172(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 170(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 85(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 168(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 84(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 166(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 83(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 164(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 82(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 162(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a3, 64(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 224(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 222(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 220(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 218(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 109(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 216(sp)
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
; RV64ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 108(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 214(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 107(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 212(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 106(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 210(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v11
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v13
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 105(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 208(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v14
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v15
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 104(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 206(sp)
; RV64ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fle.h a4, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 103(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 204(sp)
; RV64ZVFHMIN-NEXT:    fle.h a5, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    fle.h a6, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 102(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 202(sp)
; RV64ZVFHMIN-NEXT:    fle.h a7, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    fle.h t0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 101(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 200(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    fle.h t1, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 100(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 198(sp)
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 99(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 196(sp)
; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
; RV64ZVFHMIN-NEXT:    xori t1, t1, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 98(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 194(sp)
; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV64ZVFHMIN-NEXT:    sb t0, 66(sp)
; RV64ZVFHMIN-NEXT:    sb a7, 67(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 68(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a5, 69(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 70(sp)
; RV64ZVFHMIN-NEXT:    sb a3, 71(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 97(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 242(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 121(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 240(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 120(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 238(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v18
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v22
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 119(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 236(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 118(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 234(sp)
; RV64ZVFHMIN-NEXT:    fle.h a4, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    fle.h a5, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 117(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 232(sp)
; RV64ZVFHMIN-NEXT:    fle.h a6, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    fle.h a7, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 116(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 230(sp)
; RV64ZVFHMIN-NEXT:    fle.h t0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    fle.h t1, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 115(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 228(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 76(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 77(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 78(sp)
; RV64ZVFHMIN-NEXT:    sb a3, 79(sp)
; RV64ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a4, a7, 1
; RV64ZVFHMIN-NEXT:    xori a5, t0, 1
; RV64ZVFHMIN-NEXT:    xori a6, t1, 1
; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
; RV64ZVFHMIN-NEXT:    sb a3, 72(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 73(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 74(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 75(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV64ZVFHMIN-NEXT:    vsm.v v12, (a1)
; RV64ZVFHMIN-NEXT:    addi sp, s0, -384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
; RV64ZVFHMIN-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    .cfi_restore ra
; RV64ZVFHMIN-NEXT:    .cfi_restore s0
; RV64ZVFHMIN-NEXT:    addi sp, sp, 384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV64ZVFHMIN-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = insertelement <64 x half> poison, half %y, i32 0
  %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
  %d = fcmp ugt <64 x half> %a, %c
  store <64 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ugt_vf_v64f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_vf_v64f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 64
; ZVFH-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfgt.vf v16, v8, fa0
; ZVFH-NEXT:    vsm.v v16, (a1)
; ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16_nonans:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    addi sp, sp, -384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
; RV32ZVFHMIN-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
; RV32ZVFHMIN-NEXT:    addi s0, sp, 384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
; RV32ZVFHMIN-NEXT:    li a2, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
; RV32ZVFHMIN-NEXT:    vse16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 176(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 174(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 172(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 170(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 85(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 168(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 84(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 166(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 83(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 164(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 82(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 162(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a3, 64(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 224(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 222(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 220(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 218(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 109(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 216(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 108(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 214(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 107(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 212(sp)
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 106(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 210(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 105(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 208(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 104(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 206(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v11
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 103(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 204(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v13
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v14
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v15
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 102(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 202(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    sb a0, 101(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 200(sp)
; RV32ZVFHMIN-NEXT:    flt.h a4, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    flt.h a5, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    sb a0, 100(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 198(sp)
; RV32ZVFHMIN-NEXT:    flt.h a6, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    flt.h a7, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    sb a0, 99(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 196(sp)
; RV32ZVFHMIN-NEXT:    flt.h t0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    flt.h t1, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 98(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 194(sp)
; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV32ZVFHMIN-NEXT:    sb t0, 66(sp)
; RV32ZVFHMIN-NEXT:    sb a7, 67(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 68(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a5, 69(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 70(sp)
; RV32ZVFHMIN-NEXT:    sb a3, 71(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 97(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 242(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 121(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 240(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 120(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 238(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v18
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v22
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 119(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 236(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    sb a0, 118(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 234(sp)
; RV32ZVFHMIN-NEXT:    flt.h a4, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    flt.h a5, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    sb a0, 117(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 232(sp)
; RV32ZVFHMIN-NEXT:    flt.h a6, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    flt.h a7, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    sb a0, 116(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 230(sp)
; RV32ZVFHMIN-NEXT:    flt.h t0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    flt.h t1, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV32ZVFHMIN-NEXT:    sb a0, 115(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 228(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 76(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 77(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 78(sp)
; RV32ZVFHMIN-NEXT:    sb a3, 79(sp)
; RV32ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a3, 72(sp)
; RV32ZVFHMIN-NEXT:    sb t1, 73(sp)
; RV32ZVFHMIN-NEXT:    sb t0, 74(sp)
; RV32ZVFHMIN-NEXT:    sb a7, 75(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV32ZVFHMIN-NEXT:    vsm.v v12, (a1)
; RV32ZVFHMIN-NEXT:    addi sp, s0, -384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
; RV32ZVFHMIN-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    .cfi_restore ra
; RV32ZVFHMIN-NEXT:    .cfi_restore s0
; RV32ZVFHMIN-NEXT:    addi sp, sp, 384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16_nonans:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    addi sp, sp, -384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
; RV64ZVFHMIN-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
; RV64ZVFHMIN-NEXT:    addi s0, sp, 384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
; RV64ZVFHMIN-NEXT:    li a2, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
; RV64ZVFHMIN-NEXT:    vse16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 176(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 174(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 172(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 170(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 85(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 168(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 84(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 166(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 83(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 164(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 82(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 162(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a3, 64(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 224(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 222(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 220(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 218(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 109(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 216(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 108(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 214(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 107(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 212(sp)
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 106(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 210(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 105(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 208(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 104(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 206(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v11
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 103(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 204(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v13
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v14
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v15
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 102(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 202(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    sb a0, 101(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 200(sp)
; RV64ZVFHMIN-NEXT:    flt.h a4, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    flt.h a5, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    sb a0, 100(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 198(sp)
; RV64ZVFHMIN-NEXT:    flt.h a6, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    flt.h a7, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    sb a0, 99(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 196(sp)
; RV64ZVFHMIN-NEXT:    flt.h t0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    flt.h t1, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 98(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 194(sp)
; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV64ZVFHMIN-NEXT:    sb t0, 66(sp)
; RV64ZVFHMIN-NEXT:    sb a7, 67(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 68(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a5, 69(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 70(sp)
; RV64ZVFHMIN-NEXT:    sb a3, 71(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 97(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 242(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 121(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 240(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 120(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 238(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v18
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v22
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 119(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 236(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    sb a0, 118(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 234(sp)
; RV64ZVFHMIN-NEXT:    flt.h a4, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    flt.h a5, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    sb a0, 117(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 232(sp)
; RV64ZVFHMIN-NEXT:    flt.h a6, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    flt.h a7, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    sb a0, 116(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 230(sp)
; RV64ZVFHMIN-NEXT:    flt.h t0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    flt.h t1, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV64ZVFHMIN-NEXT:    sb a0, 115(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 228(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 76(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 77(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 78(sp)
; RV64ZVFHMIN-NEXT:    sb a3, 79(sp)
; RV64ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a3, 72(sp)
; RV64ZVFHMIN-NEXT:    sb t1, 73(sp)
; RV64ZVFHMIN-NEXT:    sb t0, 74(sp)
; RV64ZVFHMIN-NEXT:    sb a7, 75(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV64ZVFHMIN-NEXT:    vsm.v v12, (a1)
; RV64ZVFHMIN-NEXT:    addi sp, s0, -384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
; RV64ZVFHMIN-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    .cfi_restore ra
; RV64ZVFHMIN-NEXT:    .cfi_restore s0
; RV64ZVFHMIN-NEXT:    addi sp, sp, 384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV64ZVFHMIN-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = insertelement <64 x half> poison, half %y, i32 0
  %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
  %d = fcmp nnan ugt <64 x half> %a, %c
  store <64 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ueq_vf_v32f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_vf_v32f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a2, 32
; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v16, v8, fa0
; CHECK-NEXT:    vmfgt.vf v17, v8, fa0
; CHECK-NEXT:    vmnor.mm v8, v17, v16
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = insertelement <32 x float> poison, float %y, i32 0
  %c = shufflevector <32 x float> %b, <32 x float> poison, <32 x i32> zeroinitializer
  %d = fcmp ueq <32 x float> %a, %c
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ueq_vf_v32f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_vf_v32f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a2, 32
; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfeq.vf v16, v8, fa0
; CHECK-NEXT:    vsm.v v16, (a1)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = insertelement <32 x float> poison, float %y, i32 0
  %c = shufflevector <32 x float> %b, <32 x float> poison, <32 x i32> zeroinitializer
  %d = fcmp nnan ueq <32 x float> %a, %c
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_one_vf_v8f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_one_vf_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v16, v8, fa0
; CHECK-NEXT:    vmfgt.vf v17, v8, fa0
; CHECK-NEXT:    vmor.mm v8, v17, v16
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = insertelement <16 x double> poison, double %y, i32 0
  %c = shufflevector <16 x double> %b, <16 x double> poison, <16 x i32> zeroinitializer
  %d = fcmp one <16 x double> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_one_vf_v8f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_one_vf_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v16, v8, fa0
; CHECK-NEXT:    vsm.v v16, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = insertelement <16 x double> poison, double %y, i32 0
  %c = shufflevector <16 x double> %b, <16 x double> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan one <16 x double> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ord_vf_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ord_vf_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vfmv.v.f v9, fa0
; ZVFH-NEXT:    vmfeq.vf v9, v9, fa0
; ZVFH-NEXT:    vmfeq.vv v8, v8, v8
; ZVFH-NEXT:    vmand.mm v0, v8, v9
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ord_vf_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v9, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v9, v10, v10
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v8, v10, v10
; ZVFHMIN-NEXT:    vmand.mm v0, v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <4 x half>, ptr %x
  %b = insertelement <4 x half> poison, half %y, i32 0
  %c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer
  %d = fcmp ord <4 x half> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uno_vf_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_uno_vf_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vfmv.v.f v9, fa0
; ZVFH-NEXT:    vmfne.vf v9, v9, fa0
; ZVFH-NEXT:    vmfne.vv v8, v8, v8
; ZVFH-NEXT:    vmor.mm v0, v8, v9
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_uno_vf_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v9, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v9, v10, v10
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v8, v10, v10
; ZVFHMIN-NEXT:    vmor.mm v0, v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <2 x half>, ptr %x
  %b = insertelement <2 x half> poison, half %y, i32 0
  %c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer
  %d = fcmp uno <2 x half> %a, %c
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oeq_fv_v8f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_fv_v8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfeq.vf v8, v8, fa0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_fv_v8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v12, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT:    vsm.v v12, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = insertelement <8 x half> poison, half %y, i32 0
  %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
  %d = fcmp oeq <8 x half> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oeq_fv_v8f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_fv_v8f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfeq.vf v8, v8, fa0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_fv_v8f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v12, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT:    vsm.v v12, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = insertelement <8 x half> poison, half %y, i32 0
  %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan oeq <8 x half> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_une_fv_v4f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = insertelement <4 x float> poison, float %y, i32 0
  %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
  %d = fcmp une <4 x float> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_une_fv_v4f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = insertelement <4 x float> poison, float %y, i32 0
  %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
  %d = fcmp nnan une <4 x float> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ogt_fv_v2f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = insertelement <2 x double> poison, double %y, i32 0
  %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
  %d = fcmp ogt <2 x double> %c, %a
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ogt_fv_v2f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = insertelement <2 x double> poison, double %y, i32 0
  %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
  %d = fcmp nnan ogt <2 x double> %c, %a
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_olt_fv_v16f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_fv_v16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfgt.vf v10, v8, fa0
; ZVFH-NEXT:    vsm.v v10, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_fv_v16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v16, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT:    vsm.v v16, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = insertelement <16 x half> poison, half %y, i32 0
  %c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
  %d = fcmp olt <16 x half> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_olt_fv_v16f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_fv_v16f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfgt.vf v10, v8, fa0
; ZVFH-NEXT:    vsm.v v10, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_fv_v16f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v16, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT:    vsm.v v16, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = insertelement <16 x half> poison, half %y, i32 0
  %c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan olt <16 x half> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oge_fv_v8f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_fv_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v10, v8, fa0
; CHECK-NEXT:    vsm.v v10, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = insertelement <8 x float> poison, float %y, i32 0
  %c = shufflevector <8 x float> %b, <8 x float> poison, <8 x i32> zeroinitializer
  %d = fcmp oge <8 x float> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oge_fv_v8f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_fv_v8f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v10, v8, fa0
; CHECK-NEXT:    vsm.v v10, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = insertelement <8 x float> poison, float %y, i32 0
  %c = shufflevector <8 x float> %b, <8 x float> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan oge <8 x float> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ole_fv_v4f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_fv_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = insertelement <4 x double> poison, double %y, i32 0
  %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
  %d = fcmp ole <4 x double> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ole_fv_v4f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = insertelement <4 x double> poison, double %y, i32 0
  %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
  %d = fcmp nnan ole <4 x double> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ule_fv_v32f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_fv_v32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 32
; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmflt.vf v12, v8, fa0
; ZVFH-NEXT:    vmnot.m v8, v12
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_fv_v32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a2, 32
; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v24, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v24, v8, v16
; ZVFHMIN-NEXT:    vmnot.m v8, v24
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = insertelement <32 x half> poison, half %y, i32 0
  %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
  %d = fcmp ule <32 x half> %c, %a
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ule_fv_v32f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_fv_v32f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 32
; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfge.vf v12, v8, fa0
; ZVFH-NEXT:    vsm.v v12, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_fv_v32f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a2, 32
; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v24, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmfle.vv v24, v16, v8
; ZVFHMIN-NEXT:    vsm.v v24, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = insertelement <32 x half> poison, half %y, i32 0
  %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
  %d = fcmp nnan ule <32 x half> %c, %a
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uge_fv_v16f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_fv_v16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v12, v8, fa0
; CHECK-NEXT:    vmnot.m v8, v12
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = insertelement <16 x float> poison, float %y, i32 0
  %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
  %d = fcmp uge <16 x float> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uge_fv_v16f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_fv_v16f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v12, v8, fa0
; CHECK-NEXT:    vsm.v v12, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = insertelement <16 x float> poison, float %y, i32 0
  %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan uge <16 x float> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ult_fv_v8f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_fv_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v12, v8, fa0
; CHECK-NEXT:    vmnot.m v8, v12
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = insertelement <8 x double> poison, double %y, i32 0
  %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
  %d = fcmp ult <8 x double> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ult_fv_v8f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_fv_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v12, v8, fa0
; CHECK-NEXT:    vsm.v v12, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = insertelement <8 x double> poison, double %y, i32 0
  %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan ult <8 x double> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ugt_fv_v64f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_fv_v64f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 64
; ZVFH-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfge.vf v16, v8, fa0
; ZVFH-NEXT:    vmnot.m v8, v16
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    addi sp, sp, -384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
; RV32ZVFHMIN-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
; RV32ZVFHMIN-NEXT:    addi s0, sp, 384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
; RV32ZVFHMIN-NEXT:    li a2, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
; RV32ZVFHMIN-NEXT:    vse16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 176(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 174(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 172(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 170(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 85(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 168(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 84(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 166(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 83(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 164(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 82(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 162(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a3, 64(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 224(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 222(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 220(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 218(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 109(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 216(sp)
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
; RV32ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 108(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 214(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 107(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 212(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 106(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 210(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v11
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v13
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 105(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 208(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v14
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v15
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 104(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 206(sp)
; RV32ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    fle.h a4, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 103(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 204(sp)
; RV32ZVFHMIN-NEXT:    fle.h a5, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    fle.h a6, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 102(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 202(sp)
; RV32ZVFHMIN-NEXT:    fle.h a7, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    fle.h t0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 101(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 200(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    fle.h t1, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 100(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 198(sp)
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 99(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 196(sp)
; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
; RV32ZVFHMIN-NEXT:    xori t1, t1, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 98(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 194(sp)
; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV32ZVFHMIN-NEXT:    sb t0, 66(sp)
; RV32ZVFHMIN-NEXT:    sb a7, 67(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 68(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a5, 69(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 70(sp)
; RV32ZVFHMIN-NEXT:    sb a3, 71(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 97(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 242(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 121(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 240(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 120(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 238(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v18
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v22
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 119(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 236(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 118(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 234(sp)
; RV32ZVFHMIN-NEXT:    fle.h a4, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    fle.h a5, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 117(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 232(sp)
; RV32ZVFHMIN-NEXT:    fle.h a6, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    fle.h a7, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 116(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 230(sp)
; RV32ZVFHMIN-NEXT:    fle.h t0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    fle.h t1, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 115(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 228(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 76(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 77(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 78(sp)
; RV32ZVFHMIN-NEXT:    sb a3, 79(sp)
; RV32ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a4, a7, 1
; RV32ZVFHMIN-NEXT:    xori a5, t0, 1
; RV32ZVFHMIN-NEXT:    xori a6, t1, 1
; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
; RV32ZVFHMIN-NEXT:    sb a3, 72(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 73(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 74(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 75(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV32ZVFHMIN-NEXT:    vsm.v v12, (a1)
; RV32ZVFHMIN-NEXT:    addi sp, s0, -384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
; RV32ZVFHMIN-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    .cfi_restore ra
; RV32ZVFHMIN-NEXT:    .cfi_restore s0
; RV32ZVFHMIN-NEXT:    addi sp, sp, 384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    addi sp, sp, -384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
; RV64ZVFHMIN-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
; RV64ZVFHMIN-NEXT:    addi s0, sp, 384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
; RV64ZVFHMIN-NEXT:    li a2, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
; RV64ZVFHMIN-NEXT:    vse16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 176(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 174(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 172(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 170(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 85(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 168(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 84(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 166(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 83(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 164(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 82(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 162(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a3, 64(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 224(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 222(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 220(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 218(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 109(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 216(sp)
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
; RV64ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 108(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 214(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 107(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 212(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 106(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 210(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v11
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v13
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 105(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 208(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v14
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v15
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 104(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 206(sp)
; RV64ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    fle.h a4, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 103(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 204(sp)
; RV64ZVFHMIN-NEXT:    fle.h a5, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    fle.h a6, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 102(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 202(sp)
; RV64ZVFHMIN-NEXT:    fle.h a7, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    fle.h t0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 101(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 200(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    fle.h t1, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 100(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 198(sp)
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 99(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 196(sp)
; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
; RV64ZVFHMIN-NEXT:    xori t1, t1, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 98(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 194(sp)
; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV64ZVFHMIN-NEXT:    sb t0, 66(sp)
; RV64ZVFHMIN-NEXT:    sb a7, 67(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 68(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a5, 69(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 70(sp)
; RV64ZVFHMIN-NEXT:    sb a3, 71(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 97(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 242(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 121(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 240(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 120(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 238(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v18
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v22
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 119(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 236(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 118(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 234(sp)
; RV64ZVFHMIN-NEXT:    fle.h a4, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    fle.h a5, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 117(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 232(sp)
; RV64ZVFHMIN-NEXT:    fle.h a6, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    fle.h a7, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 116(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 230(sp)
; RV64ZVFHMIN-NEXT:    fle.h t0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    fle.h t1, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 115(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 228(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 76(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 77(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 78(sp)
; RV64ZVFHMIN-NEXT:    sb a3, 79(sp)
; RV64ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a4, a7, 1
; RV64ZVFHMIN-NEXT:    xori a5, t0, 1
; RV64ZVFHMIN-NEXT:    xori a6, t1, 1
; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
; RV64ZVFHMIN-NEXT:    sb a3, 72(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 73(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 74(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 75(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV64ZVFHMIN-NEXT:    vsm.v v12, (a1)
; RV64ZVFHMIN-NEXT:    addi sp, s0, -384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
; RV64ZVFHMIN-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    .cfi_restore ra
; RV64ZVFHMIN-NEXT:    .cfi_restore s0
; RV64ZVFHMIN-NEXT:    addi sp, sp, 384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV64ZVFHMIN-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = insertelement <64 x half> poison, half %y, i32 0
  %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
  %d = fcmp ugt <64 x half> %c, %a
  store <64 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ugt_fv_v64f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_fv_v64f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 64
; ZVFH-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmflt.vf v16, v8, fa0
; ZVFH-NEXT:    vsm.v v16, (a1)
; ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16_nonans:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    addi sp, sp, -384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
; RV32ZVFHMIN-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
; RV32ZVFHMIN-NEXT:    addi s0, sp, 384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
; RV32ZVFHMIN-NEXT:    li a2, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
; RV32ZVFHMIN-NEXT:    vse16.v v8, (a0)
; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 176(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 174(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 172(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 170(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 85(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 168(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 84(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 166(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 83(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 164(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 82(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 162(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a3, 64(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 224(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 222(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 220(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 218(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 109(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 216(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 108(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 214(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 107(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 212(sp)
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 106(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 210(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 105(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 208(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 104(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 206(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v11
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 103(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 204(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v13
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v14
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v15
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 102(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 202(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    sb a0, 101(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 200(sp)
; RV32ZVFHMIN-NEXT:    flt.h a4, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    flt.h a5, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    sb a0, 100(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 198(sp)
; RV32ZVFHMIN-NEXT:    flt.h a6, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    flt.h a7, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    sb a0, 99(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 196(sp)
; RV32ZVFHMIN-NEXT:    flt.h t0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    flt.h t1, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 98(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 194(sp)
; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV32ZVFHMIN-NEXT:    sb t0, 66(sp)
; RV32ZVFHMIN-NEXT:    sb a7, 67(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 68(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a5, 69(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 70(sp)
; RV32ZVFHMIN-NEXT:    sb a3, 71(sp)
; RV32ZVFHMIN-NEXT:    sb a0, 97(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 242(sp)
; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 121(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 240(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v12
; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v16
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 120(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 238(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v18
; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v22
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 119(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 236(sp)
; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v8
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV32ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV32ZVFHMIN-NEXT:    sb a0, 118(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 234(sp)
; RV32ZVFHMIN-NEXT:    flt.h a4, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV32ZVFHMIN-NEXT:    flt.h a5, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV32ZVFHMIN-NEXT:    sb a0, 117(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 232(sp)
; RV32ZVFHMIN-NEXT:    flt.h a6, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV32ZVFHMIN-NEXT:    flt.h a7, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV32ZVFHMIN-NEXT:    sb a0, 116(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 230(sp)
; RV32ZVFHMIN-NEXT:    flt.h t0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV32ZVFHMIN-NEXT:    flt.h t1, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV32ZVFHMIN-NEXT:    sb a0, 115(sp)
; RV32ZVFHMIN-NEXT:    lh a0, 228(sp)
; RV32ZVFHMIN-NEXT:    sb a6, 76(sp)
; RV32ZVFHMIN-NEXT:    sb a5, 77(sp)
; RV32ZVFHMIN-NEXT:    sb a4, 78(sp)
; RV32ZVFHMIN-NEXT:    sb a3, 79(sp)
; RV32ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a3, 72(sp)
; RV32ZVFHMIN-NEXT:    sb t1, 73(sp)
; RV32ZVFHMIN-NEXT:    sb t0, 74(sp)
; RV32ZVFHMIN-NEXT:    sb a7, 75(sp)
; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV32ZVFHMIN-NEXT:    vsm.v v12, (a1)
; RV32ZVFHMIN-NEXT:    addi sp, s0, -384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
; RV32ZVFHMIN-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
; RV32ZVFHMIN-NEXT:    .cfi_restore ra
; RV32ZVFHMIN-NEXT:    .cfi_restore s0
; RV32ZVFHMIN-NEXT:    addi sp, sp, 384
; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16_nonans:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    addi sp, sp, -384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
; RV64ZVFHMIN-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
; RV64ZVFHMIN-NEXT:    addi s0, sp, 384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
; RV64ZVFHMIN-NEXT:    li a2, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
; RV64ZVFHMIN-NEXT:    vse16.v v8, (a0)
; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 176(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 174(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 172(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 170(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 85(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 168(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 84(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 166(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 83(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 164(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 82(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 162(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a3, 64(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 224(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 222(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 220(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 218(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 109(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 216(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 108(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 214(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 107(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 212(sp)
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 106(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 210(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 105(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 208(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 104(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 206(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v11
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 103(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 204(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v13
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v14
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v15
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 102(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 202(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    sb a0, 101(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 200(sp)
; RV64ZVFHMIN-NEXT:    flt.h a4, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    flt.h a5, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    sb a0, 100(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 198(sp)
; RV64ZVFHMIN-NEXT:    flt.h a6, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    flt.h a7, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    sb a0, 99(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 196(sp)
; RV64ZVFHMIN-NEXT:    flt.h t0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    flt.h t1, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 98(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 194(sp)
; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
; RV64ZVFHMIN-NEXT:    sb t0, 66(sp)
; RV64ZVFHMIN-NEXT:    sb a7, 67(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 68(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a5, 69(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 70(sp)
; RV64ZVFHMIN-NEXT:    sb a3, 71(sp)
; RV64ZVFHMIN-NEXT:    sb a0, 97(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 242(sp)
; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 121(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 240(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v12
; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v16
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 120(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 238(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v18
; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v22
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 119(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 236(sp)
; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v8
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
; RV64ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
; RV64ZVFHMIN-NEXT:    sb a0, 118(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 234(sp)
; RV64ZVFHMIN-NEXT:    flt.h a4, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
; RV64ZVFHMIN-NEXT:    flt.h a5, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
; RV64ZVFHMIN-NEXT:    sb a0, 117(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 232(sp)
; RV64ZVFHMIN-NEXT:    flt.h a6, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
; RV64ZVFHMIN-NEXT:    flt.h a7, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
; RV64ZVFHMIN-NEXT:    sb a0, 116(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 230(sp)
; RV64ZVFHMIN-NEXT:    flt.h t0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
; RV64ZVFHMIN-NEXT:    flt.h t1, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
; RV64ZVFHMIN-NEXT:    sb a0, 115(sp)
; RV64ZVFHMIN-NEXT:    lh a0, 228(sp)
; RV64ZVFHMIN-NEXT:    sb a6, 76(sp)
; RV64ZVFHMIN-NEXT:    sb a5, 77(sp)
; RV64ZVFHMIN-NEXT:    sb a4, 78(sp)
; RV64ZVFHMIN-NEXT:    sb a3, 79(sp)
; RV64ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a3, 72(sp)
; RV64ZVFHMIN-NEXT:    sb t1, 73(sp)
; RV64ZVFHMIN-NEXT:    sb t0, 74(sp)
; RV64ZVFHMIN-NEXT:    sb a7, 75(sp)
; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
; RV64ZVFHMIN-NEXT:    vsm.v v12, (a1)
; RV64ZVFHMIN-NEXT:    addi sp, s0, -384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
; RV64ZVFHMIN-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
; RV64ZVFHMIN-NEXT:    .cfi_restore ra
; RV64ZVFHMIN-NEXT:    .cfi_restore s0
; RV64ZVFHMIN-NEXT:    addi sp, sp, 384
; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
; RV64ZVFHMIN-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = insertelement <64 x half> poison, half %y, i32 0
  %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
  %d = fcmp nnan ugt <64 x half> %c, %a
  store <64 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ueq_fv_v32f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_fv_v32f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a2, 32
; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v16, v8, fa0
; CHECK-NEXT:    vmflt.vf v17, v8, fa0
; CHECK-NEXT:    vmnor.mm v8, v17, v16
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = insertelement <32 x float> poison, float %y, i32 0
  %c = shufflevector <32 x float> %b, <32 x float> poison, <32 x i32> zeroinitializer
  %d = fcmp ueq <32 x float> %c, %a
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ueq_fv_v32f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_fv_v32f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a2, 32
; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfeq.vf v16, v8, fa0
; CHECK-NEXT:    vsm.v v16, (a1)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = insertelement <32 x float> poison, float %y, i32 0
  %c = shufflevector <32 x float> %b, <32 x float> poison, <32 x i32> zeroinitializer
  %d = fcmp nnan ueq <32 x float> %c, %a
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_one_fv_v8f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_one_fv_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v16, v8, fa0
; CHECK-NEXT:    vmflt.vf v17, v8, fa0
; CHECK-NEXT:    vmor.mm v8, v17, v16
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = insertelement <16 x double> poison, double %y, i32 0
  %c = shufflevector <16 x double> %b, <16 x double> poison, <16 x i32> zeroinitializer
  %d = fcmp one <16 x double> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_one_fv_v8f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_one_fv_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v16, v8, fa0
; CHECK-NEXT:    vsm.v v16, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = insertelement <16 x double> poison, double %y, i32 0
  %c = shufflevector <16 x double> %b, <16 x double> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan one <16 x double> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ord_fv_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ord_fv_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vfmv.v.f v9, fa0
; ZVFH-NEXT:    vmfeq.vf v9, v9, fa0
; ZVFH-NEXT:    vmfeq.vv v8, v8, v8
; ZVFH-NEXT:    vmand.mm v0, v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ord_fv_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v9, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v9, v10, v10
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v8, v10, v10
; ZVFHMIN-NEXT:    vmand.mm v0, v9, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <4 x half>, ptr %x
  %b = insertelement <4 x half> poison, half %y, i32 0
  %c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer
  %d = fcmp ord <4 x half> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uno_fv_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_uno_fv_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vfmv.v.f v9, fa0
; ZVFH-NEXT:    vmfne.vf v9, v9, fa0
; ZVFH-NEXT:    vmfne.vv v8, v8, v8
; ZVFH-NEXT:    vmor.mm v0, v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_uno_fv_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v9, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v9, v10, v10
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v8, v10, v10
; ZVFHMIN-NEXT:    vmor.mm v0, v9, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <2 x half>, ptr %x
  %b = insertelement <2 x half> poison, half %y, i32 0
  %c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer
  %d = fcmp uno <2 x half> %c, %a
  store <2 x i1> %d, ptr %z
  ret void
}