; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa,+v \
; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa,+v \
; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s

define <1 x bfloat> @v1bf16(<1 x bfloat> %v) {
; CHECK-LABEL: v1bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <1 x bfloat> @llvm.fabs.v1bf16(<1 x bfloat> %v)
  ret <1 x bfloat> %r
}

define <2 x bfloat> @v2bf16(<2 x bfloat> %v) {
; CHECK-LABEL: v2bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %v)
  ret <2 x bfloat> %r
}

define <4 x bfloat> @v4bf16(<4 x bfloat> %v) {
; CHECK-LABEL: v4bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <4 x bfloat> @llvm.fabs.v4bf16(<4 x bfloat> %v)
  ret <4 x bfloat> %r
}

define <8 x bfloat> @v8bf16(<8 x bfloat> %v) {
; CHECK-LABEL: v8bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <8 x bfloat> @llvm.fabs.v8bf16(<8 x bfloat> %v)
  ret <8 x bfloat> %r
}

define <16 x bfloat> @v16bf16(<16 x bfloat> %v) {
; CHECK-LABEL: v16bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <16 x bfloat> @llvm.fabs.v16bf16(<16 x bfloat> %v)
  ret <16 x bfloat> %r
}

define <32 x bfloat> @v32bf16(<32 x bfloat> %v) {
; CHECK-LABEL: v32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <32 x bfloat> @llvm.fabs.v32bf16(<32 x bfloat> %v)
  ret <32 x bfloat> %r
}