; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvfbfa \
; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvfbfa \
; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s

define <vscale x 1 x bfloat> @test_half_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {
; CHECK-LABEL: test_half_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fsrmi a2, 0
; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v10, v10, v11
; CHECK-NEXT:    vsetvli zero, zero, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v8, v8, v9
; CHECK-NEXT:    fsrm a2
; CHECK-NEXT:    vse16.v v10, (a1)
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
    <vscale x 1 x half> poison,
    <vscale x 1 x half> %3,
    <vscale x 1 x half> %4,
    iXLen 0, iXLen %2)

  %b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
    <vscale x 1 x bfloat> poison,
    <vscale x 1 x bfloat> %0,
    <vscale x 1 x bfloat> %1,
    iXLen 0, iXLen %2)

  call void @llvm.riscv.vse(<vscale x 1 x half> %a, ptr %ptr, iXLen %2)

  ret <vscale x 1 x bfloat> %b
}

define <vscale x 1 x bfloat> @test_i32_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i32> %3, <vscale x 1 x i32> %4, ptr %ptr) nounwind {
; CHECK-LABEL: test_i32_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT:    vadd.vv v10, v10, v11
; CHECK-NEXT:    fsrmi a0, 0
; CHECK-NEXT:    vsetvli zero, zero, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v8, v8, v9
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    vse32.v v10, (a1)
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
    <vscale x 1 x i32> poison,
    <vscale x 1 x i32> %3,
    <vscale x 1 x i32> %4,
    iXLen %2)

  %b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
    <vscale x 1 x bfloat> poison,
    <vscale x 1 x bfloat> %0,
    <vscale x 1 x bfloat> %1,
    iXLen 0, iXLen %2)

  call void @llvm.riscv.vse(<vscale x 1 x i32> %a, ptr %ptr, iXLen %2)

  ret <vscale x 1 x bfloat> %b
}

define <vscale x 1 x bfloat> @test_half_bf16_half(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {
; CHECK-LABEL: test_half_bf16_half:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fsrmi a2, 0
; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v10, v10, v11
; CHECK-NEXT:    vsetvli zero, zero, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v9, v10, v11
; CHECK-NEXT:    fsrm a2
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vse16.v v9, (a1)
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
    <vscale x 1 x half> poison,
    <vscale x 1 x half> %3,
    <vscale x 1 x half> %4,
    iXLen 0, iXLen %2)

  %b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
    <vscale x 1 x bfloat> poison,
    <vscale x 1 x bfloat> %0,
    <vscale x 1 x bfloat> %1,
    iXLen 0, iXLen %2)

  %c = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
    <vscale x 1 x half> poison,
    <vscale x 1 x half> %a,
    <vscale x 1 x half> %4,
    iXLen 0, iXLen %2)

  store <vscale x 1 x half> %c, ptr %ptr

  ret <vscale x 1 x bfloat> %b
}

define <vscale x 1 x bfloat> @test_bf16_half_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {
; CHECK-LABEL: test_bf16_half_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fsrmi a2, 0
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v10, v10, v11
; CHECK-NEXT:    vsetvli zero, zero, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v8, v8, v9
; CHECK-NEXT:    fsrm a2
; CHECK-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; CHECK-NEXT:    vse16.v v10, (a1)
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
    <vscale x 1 x bfloat> poison,
    <vscale x 1 x bfloat> %0,
    <vscale x 1 x bfloat> %1,
    iXLen 0, iXLen %2)

  %b = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
    <vscale x 1 x half> poison,
    <vscale x 1 x half> %3,
    <vscale x 1 x half> %4,
    iXLen 0, iXLen %2)

  %c = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
    <vscale x 1 x bfloat> poison,
    <vscale x 1 x bfloat> %a,
    <vscale x 1 x bfloat> %1,
    iXLen 0, iXLen %2)

  store <vscale x 1 x half> %b, ptr %ptr

  ret <vscale x 1 x bfloat> %c
}

define <vscale x 1 x bfloat> @test_bf16_i16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i16> %3, <vscale x 1 x i16> %4, ptr %ptr) nounwind {
; CHECK-LABEL: test_bf16_i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fsrmi a2, 0
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfadd.vv v8, v8, v9
; CHECK-NEXT:    vadd.vv v9, v10, v11
; CHECK-NEXT:    fsrm a2
; CHECK-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; CHECK-NEXT:    vse16.v v9, (a1)
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(
    <vscale x 1 x bfloat> poison,
    <vscale x 1 x bfloat> %0,
    <vscale x 1 x bfloat> %1,
    iXLen 0, iXLen %2)

  %b = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
    <vscale x 1 x i16> poison,
    <vscale x 1 x i16> %3,
    <vscale x 1 x i16> %4,
    iXLen %2)

  store <vscale x 1 x i16> %b, ptr %ptr

  ret <vscale x 1 x bfloat> %a
}