; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \
; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \
; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s

define <vscale x 1 x bfloat> @intrinsic_vfmerge_vfm_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1bf16_nxv1bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16(
    <vscale x 1 x bfloat> poison,
    <vscale x 1 x bfloat> %0,
    bfloat %1,
    <vscale x 1 x i1> %2,
    iXLen %3)

  ret <vscale x 1 x bfloat> %a
}

define <vscale x 2 x bfloat> @intrinsic_vfmerge_vfm_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2bf16_nxv2bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf2, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16(
    <vscale x 2 x bfloat> poison,
    <vscale x 2 x bfloat> %0,
    bfloat %1,
    <vscale x 2 x i1> %2,
    iXLen %3)

  ret <vscale x 2 x bfloat> %a
}

define <vscale x 4 x bfloat> @intrinsic_vfmerge_vfm_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4bf16_nxv4bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m1, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16(
    <vscale x 4 x bfloat> poison,
    <vscale x 4 x bfloat> %0,
    bfloat %1,
    <vscale x 4 x i1> %2,
    iXLen %3)

  ret <vscale x 4 x bfloat> %a
}

define <vscale x 8 x bfloat> @intrinsic_vfmerge_vfm_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8bf16_nxv8bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m2, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16(
    <vscale x 8 x bfloat> poison,
    <vscale x 8 x bfloat> %0,
    bfloat %1,
    <vscale x 8 x i1> %2,
    iXLen %3)

  ret <vscale x 8 x bfloat> %a
}

define <vscale x 16 x bfloat> @intrinsic_vfmerge_vfm_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16bf16_nxv16bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16(
    <vscale x 16 x bfloat> poison,
    <vscale x 16 x bfloat> %0,
    bfloat %1,
    <vscale x 16 x i1> %2,
    iXLen %3)

  ret <vscale x 16 x bfloat> %a
}

define <vscale x 32 x bfloat> @intrinsic_vfmerge_vfm_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv32bf16_nxv32bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m8, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16(
    <vscale x 32 x bfloat> poison,
    <vscale x 32 x bfloat> %0,
    bfloat %1,
    <vscale x 32 x i1> %2,
    iXLen %3)

  ret <vscale x 32 x bfloat> %a
}

define <vscale x 1 x bfloat> @intrinsic_vfmerge_vzm_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1bf16_nxv1bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fmv.h.x fa5, zero
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa5, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16(
    <vscale x 1 x bfloat> poison,
    <vscale x 1 x bfloat> %0,
    bfloat zeroinitializer,
    <vscale x 1 x i1> %1,
    iXLen %2)

  ret <vscale x 1 x bfloat> %a
}

define <vscale x 2 x bfloat> @intrinsic_vfmerge_vzm_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2bf16_nxv2bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fmv.h.x fa5, zero
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf2, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa5, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16(
    <vscale x 2 x bfloat> poison,
    <vscale x 2 x bfloat> %0,
    bfloat zeroinitializer,
    <vscale x 2 x i1> %1,
    iXLen %2)

  ret <vscale x 2 x bfloat> %a
}

define <vscale x 4 x bfloat> @intrinsic_vfmerge_vzm_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4bf16_nxv4bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fmv.h.x fa5, zero
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m1, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa5, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16(
    <vscale x 4 x bfloat> poison,
    <vscale x 4 x bfloat> %0,
    bfloat zeroinitializer,
    <vscale x 4 x i1> %1,
    iXLen %2)

  ret <vscale x 4 x bfloat> %a
}

define <vscale x 8 x bfloat> @intrinsic_vfmerge_vzm_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8bf16_nxv8bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fmv.h.x fa5, zero
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m2, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa5, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16(
    <vscale x 8 x bfloat> poison,
    <vscale x 8 x bfloat> %0,
    bfloat zeroinitializer,
    <vscale x 8 x i1> %1,
    iXLen %2)

  ret <vscale x 8 x bfloat> %a
}

define <vscale x 16 x bfloat> @intrinsic_vfmerge_vzm_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16bf16_nxv16bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fmv.h.x fa5, zero
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa5, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16(
    <vscale x 16 x bfloat> poison,
    <vscale x 16 x bfloat> %0,
    bfloat zeroinitializer,
    <vscale x 16 x i1> %1,
    iXLen %2)

  ret <vscale x 16 x bfloat> %a
}

define <vscale x 32 x bfloat> @intrinsic_vfmerge_vzm_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32bf16_nxv32bf16_bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    fmv.h.x fa5, zero
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m8, ta, ma
; CHECK-NEXT:    vfmerge.vfm v8, v8, fa5, v0
; CHECK-NEXT:    ret
entry:
  %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16(
    <vscale x 32 x bfloat> poison,
    <vscale x 32 x bfloat> %0,
    bfloat zeroinitializer,
    <vscale x 32 x i1> %1,
    iXLen %2)

  ret <vscale x 32 x bfloat> %a
}