; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -o - %s | FileCheck %s

define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-LABEL: test_vaddq_f16:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vadd.f16 q0, q0, q1
; CHECK-NEXT:    bx lr
entry:
  %0 = tail call <8 x half> @llvm.arm.mve.vadd.v8f16(<8 x half> %a, <8 x half> %b)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32(<4 x float> %a, <4 x float> %b) #0 {
; CHECK-LABEL: test_vaddq_f32:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vadd.f32 q0, q0, q1
; CHECK-NEXT:    bx lr
entry:
  %0 = tail call <4 x float> @llvm.arm.mve.vadd.v4f32(<4 x float> %a, <4 x float> %b)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-LABEL: test_vsubq_f16:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vsub.f16 q0, q0, q1
; CHECK-NEXT:    bx lr
entry:
  %0 = tail call <8 x half> @llvm.arm.mve.vsub.v8f16(<8 x half> %a, <8 x half> %b)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @test_vsubq_f32(<4 x float> %a, <4 x float> %b) #0 {
; CHECK-LABEL: test_vsubq_f32:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vsub.f32 q0, q0, q1
; CHECK-NEXT:    bx lr
entry:
  %0 = tail call <4 x float> @llvm.arm.mve.vsub.v4f32(<4 x float> %a, <4 x float> %b)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @test_vmulq_f16(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-LABEL: test_vmulq_f16:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmul.f16 q0, q0, q1
; CHECK-NEXT:    bx lr
entry:
  %0 = tail call <8 x half> @llvm.arm.mve.vmul.v8f16(<8 x half> %a, <8 x half> %b)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> %a, <4 x float> %b) #0 {
; CHECK-LABEL: test_vmulq_f32:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmul.f32 q0, q0, q1
; CHECK-NEXT:    bx lr
entry:
  %0 = tail call <4 x float> @llvm.arm.mve.vmul.v4f32(<4 x float> %a, <4 x float> %b)
  ret <4 x float> %0
}




define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16_splat(<8 x half> %a, half %b) #0 {
; CHECK-LABEL: test_vaddq_f16_splat:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov.f16 r0, s4
; CHECK-NEXT:    vadd.f16 q0, q0, r0
; CHECK-NEXT:    bx lr
entry:
  %i = insertelement <8 x half> poison, half %b, i32 0
  %s = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer
  %0 = tail call <8 x half> @llvm.arm.mve.vadd.v8f16(<8 x half> %a, <8 x half> %s)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32_splat(<4 x float> %a, float %b) #0 {
; CHECK-LABEL: test_vaddq_f32_splat:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov r0, s4
; CHECK-NEXT:    vadd.f32 q0, q0, r0
; CHECK-NEXT:    bx lr
entry:
  %i = insertelement <4 x float> poison, float %b, i32 0
  %s = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer
  %0 = tail call <4 x float> @llvm.arm.mve.vadd.v4f32(<4 x float> %a, <4 x float> %s)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16_splat(<8 x half> %a, half %b) #0 {
; CHECK-LABEL: test_vsubq_f16_splat:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov.f16 r0, s4
; CHECK-NEXT:    vsub.f16 q0, q0, r0
; CHECK-NEXT:    bx lr
entry:
  %i = insertelement <8 x half> poison, half %b, i32 0
  %s = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer
  %0 = tail call <8 x half> @llvm.arm.mve.vsub.v8f16(<8 x half> %a, <8 x half> %s)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @test_vsubq_f32_splat(<4 x float> %a, float %b) #0 {
; CHECK-LABEL: test_vsubq_f32_splat:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov r0, s4
; CHECK-NEXT:    vsub.f32 q0, q0, r0
; CHECK-NEXT:    bx lr
entry:
  %i = insertelement <4 x float> poison, float %b, i32 0
  %s = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer
  %0 = tail call <4 x float> @llvm.arm.mve.vsub.v4f32(<4 x float> %a, <4 x float> %s)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @test_vmulq_f16_splat(<8 x half> %a, half %b) #0 {
; CHECK-LABEL: test_vmulq_f16_splat:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov.f16 r0, s4
; CHECK-NEXT:    vmul.f16 q0, q0, r0
; CHECK-NEXT:    bx lr
entry:
  %i = insertelement <8 x half> poison, half %b, i32 0
  %s = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer
  %0 = tail call <8 x half> @llvm.arm.mve.vmul.v8f16(<8 x half> %a, <8 x half> %s)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32_splat(<4 x float> %a, float %b) #0 {
; CHECK-LABEL: test_vmulq_f32_splat:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov r0, s4
; CHECK-NEXT:    vmul.f32 q0, q0, r0
; CHECK-NEXT:    bx lr
entry:
  %i = insertelement <4 x float> poison, float %b, i32 0
  %s = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer
  %0 = tail call <4 x float> @llvm.arm.mve.vmul.v4f32(<4 x float> %a, <4 x float> %s)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <4 x float> @fma_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) #0 {
; CHECK-LABEL: fma_v4f32:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vfma.f32 q0, q1, q2
; CHECK-NEXT:    bx lr
entry:
  %0 = tail call <4 x float> @llvm.arm.mve.fma.v4f32(<4 x float> %s1, <4 x float> %s2, <4 x float> %dst)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @fma_v8f16(<8 x half> %dst, <8 x half> %s1, <8 x half> %s2) #0 {
; CHECK-LABEL: fma_v8f16:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vfma.f16 q0, q1, q2
; CHECK-NEXT:    bx lr
entry:
  %0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %s1, <8 x half> %s2, <8 x half> %dst)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @fma_n_v8f16(<4 x float> %s1, <4 x float> %s2, float %s3) #0 {
; CHECK-LABEL: fma_n_v8f16:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov r0, s8
; CHECK-NEXT:    vfma.f32 q0, q1, r0
; CHECK-NEXT:    bx lr
entry:
  %i = insertelement <4 x float> poison, float %s3, i32 0
  %sp = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer
  %0 = tail call <4 x float> @llvm.arm.mve.fma.v4f32(<4 x float> %s2, <4 x float> %sp, <4 x float> %s1)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @fma_n_v4f32(<8 x half> %s1, <8 x half> %s2, half %s3) #0 {
; CHECK-LABEL: fma_n_v4f32:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov.f16 r0, s8
; CHECK-NEXT:    vfma.f16 q0, q1, r0
; CHECK-NEXT:    bx lr
entry:
  %i = insertelement <8 x half> poison, half %s3, i32 0
  %sp = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer
  %0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %s2, <8 x half> %sp, <8 x half> %s1)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @fms_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) #0 {
; CHECK-LABEL: fms_v4f32:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vfms.f32 q0, q1, q2
; CHECK-NEXT:    bx lr
entry:
  %c = fneg <4 x float> %s1
  %0 = tail call <4 x float> @llvm.arm.mve.fma.v4f32(<4 x float> %c, <4 x float> %s2, <4 x float> %dst)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @fms_v8f16(<8 x half> %dst, <8 x half> %s1, <8 x half> %s2) #0 {
; CHECK-LABEL: fms_v8f16:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vfms.f16 q0, q1, q2
; CHECK-NEXT:    bx lr
entry:
  %c = fneg <8 x half> %s1
  %0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %c, <8 x half> %s2, <8 x half> %dst)
  ret <8 x half> %0
}

define arm_aapcs_vfpcc <4 x float> @fms_n_v8f16(<4 x float> %s1, <4 x float> %s2, float %s3) #0 {
; CHECK-LABEL: fms_n_v8f16:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov r0, s8
; CHECK-NEXT:    vdup.32 q2, r0
; CHECK-NEXT:    vfms.f32 q0, q1, q2
; CHECK-NEXT:    bx lr
entry:
  %c = fneg <4 x float> %s2
  %i = insertelement <4 x float> poison, float %s3, i32 0
  %sp = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer
  %0 = tail call <4 x float> @llvm.arm.mve.fma.v4f32(<4 x float> %c, <4 x float> %sp, <4 x float> %s1)
  ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @fms_n_v4f32(<8 x half> %s1, <8 x half> %s2, half %s3) #0 {
; CHECK-LABEL: fms_n_v4f32:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov.f16 r0, s8
; CHECK-NEXT:    vdup.16 q2, r0
; CHECK-NEXT:    vfms.f16 q0, q1, q2
; CHECK-NEXT:    bx lr
entry:
  %c = fneg <8 x half> %s2
  %i = insertelement <8 x half> poison, half %s3, i32 0
  %sp = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer
  %0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %c, <8 x half> %sp, <8 x half> %s1)
  ret <8 x half> %0
}

attributes #0 = { strictfp }