; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN:  opt -passes="gvn-sink" -S %s | FileCheck %s

;; See https://github.com/llvm/llvm-project/issues/138345 for details.
;; The program below used to crash due to taking the address of the inline asm.
;; gvn-sink shouldn't do anything in this case, so test that the pass no longer
;; generates invalid IR and no longer crashes.

define void @c(i64 %num, ptr %ptr) {
; CHECK-LABEL: define void @c(
; CHECK-SAME: i64 [[NUM:%.*]], ptr [[PTR:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    switch i64 [[NUM]], label %[[SW_EPILOG:.*]] [
; CHECK-NEXT:      i64 1, label %[[SW_BB:.*]]
; CHECK-NEXT:      i64 0, label %[[SW_BB1:.*]]
; CHECK-NEXT:    ]
; CHECK:       [[SW_BB]]:
; CHECK-NEXT:    [[TMP1:%.*]] = load i8, ptr [[PTR]], align 1
; CHECK-NEXT:    call void asm sideeffect "", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 [[TMP1]], ptr @c)
; CHECK-NEXT:    br label %[[SW_EPILOG]]
; CHECK:       [[SW_BB1]]:
; CHECK-NEXT:    [[TMP2:%.*]] = load i8, ptr [[PTR]], align 1
; CHECK-NEXT:    call void asm sideeffect "movdqu 0 [[XMM0:%.*]] \0A\09", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 [[TMP2]], ptr @c)
; CHECK-NEXT:    br label %[[SW_EPILOG]]
; CHECK:       [[SW_EPILOG]]:
; CHECK-NEXT:    ret void
;
entry:
  switch i64 %num, label %sw.epilog [
  i64 1, label %sw.bb
  i64 0, label %sw.bb1
  ]

sw.bb:                                            ; preds = %entry
  %1 = load i8, ptr %ptr, align 1
  call void asm sideeffect "", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 %1, ptr @c)
  br label %sw.epilog

sw.bb1:                                           ; preds = %entry
  %2 = load i8, ptr %ptr, align 1
  call void asm sideeffect "movdqu 0 %xmm0           \0A\09", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 %2, ptr @c)
  br label %sw.epilog

sw.epilog:                                        ; preds = %sw.bb1, %sw.bb, %entry
  ret void
}