; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 6
; RUN: opt < %s -passes=instcombine -S | FileCheck %s

define i32 @LHSBin(i1 %C) !prof !0 {
; CHECK-LABEL: define i32 @LHSBin(
; CHECK-SAME: i1 [[C:%.*]]) !prof [[PROF0:![0-9]+]] {
; CHECK-NEXT:    [[V:%.*]] = select i1 [[C]], i32 1010, i32 20, !prof [[PROF1:![0-9]+]]
; CHECK-NEXT:    ret i32 [[V]]
;
  %A = select i1 %C, i32 1000, i32 10, !prof !1
  %V = add i32 %A, 10
  ret i32 %V
}

define i32 @RHSBin(i1 %C) !prof !0 {
; CHECK-LABEL: define i32 @RHSBin(
; CHECK-SAME: i1 [[C:%.*]]) !prof [[PROF0]] {
; CHECK-NEXT:    [[V:%.*]] = select i1 [[C]], i32 1010, i32 20, !prof [[PROF1]]
; CHECK-NEXT:    ret i32 [[V]]
;
  %A = select i1 %C, i32 1000, i32 10, !prof !1
  %V = add i32 10, %A
  ret i32 %V;
}

define i32 @BothBin(i1 %C) !prof !0 {
; CHECK-LABEL: define i32 @BothBin(
; CHECK-SAME: i1 [[C:%.*]]) !prof [[PROF0]] {
; CHECK-NEXT:    [[V:%.*]] = select i1 [[C]], i32 2000, i32 20, !prof [[PROF1]]
; CHECK-NEXT:    ret i32 [[V]]
;
  %A = select i1 %C, i32 1000, i32 10, !prof !1
  %B = select i1 %C, i32 1000, i32 10, !prof !1
  %V = add i32 %A, %B
  ret i32 %V;
}

define i32 @NegBin(i1 %C) !prof !0 {
; CHECK-LABEL: define i32 @NegBin(
; CHECK-SAME: i1 [[C:%.*]]) !prof [[PROF0]] {
; CHECK-NEXT:    [[V:%.*]] = select i1 [[C]], i32 1010, i32 0, !prof [[PROF1]]
; CHECK-NEXT:    ret i32 [[V]]
;
  %A = select i1 %C, i32 1000, i32 -10, !prof !1
  %V = add i32 %A, 10
  ret i32 %V
}

define i32 @select_C_minus_1_or_C_from_bool(i1 %x) !prof !0 {
; CHECK-LABEL: define i32 @select_C_minus_1_or_C_from_bool(
; CHECK-SAME: i1 [[X:%.*]]) !prof [[PROF0]] {
; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[X]], i32 41, i32 42, !prof [[PROF2:![0-9]+]]
; CHECK-NEXT:    ret i32 [[ADD]]
;
  %ext = sext i1 %x to i32
  %add = add i32 %ext, 42
  ret i32 %add
}

define i5 @and_add(i1 %x, i1 %y) !prof !0 {
; CHECK-LABEL: define i5 @and_add(
; CHECK-SAME: i1 [[X:%.*]], i1 [[Y:%.*]]) !prof [[PROF0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = xor i1 [[X]], true
; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[Y]], [[TMP1]]
; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i5 -2, i5 0, !prof [[PROF2]]
; CHECK-NEXT:    ret i5 [[R]]
;
  %xz = zext i1 %x to i5
  %ys = sext i1 %y to i5
  %sub = add i5 %xz, %ys
  %r = and i5 %sub, 30
  ret i5 %r
}

define i32 @add_zext_zext_i1(i1 %a) !prof !0 {
; CHECK-LABEL: define i32 @add_zext_zext_i1(
; CHECK-SAME: i1 [[A:%.*]]) !prof [[PROF0]] {
; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[A]], i32 2, i32 0, !prof [[PROF2]]
; CHECK-NEXT:    ret i32 [[ADD]]
;
  %zext = zext i1 %a to i32
  %add = add i32 %zext, %zext
  ret i32 %add
}

define i32 @no_count_no_branch_weights(i1 %a) {
; CHECK-LABEL: define i32 @no_count_no_branch_weights(
; CHECK-SAME: i1 [[A:%.*]]) {
; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[A]], i32 2, i32 0
; CHECK-NEXT:    ret i32 [[ADD]]
;
  %zext = zext i1 %a to i32
  %add = add i32 %zext, %zext
  ret i32 %add
}


!0 = !{!"function_entry_count", i64 1000}
!1 = !{!"branch_weights", i32 2, i32 3}
;.
; CHECK: [[PROF0]] = !{!"function_entry_count", i64 1000}
; CHECK: [[PROF1]] = !{!"branch_weights", i32 2, i32 3}
; CHECK: [[PROF2]] = !{!"unknown", !"instcombine"}
;.