; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -passes=loop-vectorize -S -prefer-predicate-over-epilogue=scalar-epilogue < %s | FileCheck %s ; RUN: opt -passes=loop-vectorize -S -force-vector-interleave=2 -prefer-predicate-over-epilogue=scalar-epilogue < %s | FileCheck --check-prefix=IC2 %s target triple = "aarch64-unknown-linux-gnu" ; Test cases for PR60831. define void @test_invar_gep(ptr %dst) #0 { ; CHECK-LABEL: @test_invar_gep( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 100, [[TMP3]] ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 100, [[N_MOD_VF]] ; CHECK-NEXT: [[TMP5:%.*]] = call @llvm.stepvector.nxv4i64() ; CHECK-NEXT: [[TMP4:%.*]] = mul nsw [[TMP5]], splat (i64 1) ; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw zeroinitializer, [[TMP4]] ; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[TMP3]], i64 0 ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP9:%.*]] = phi [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.vscale.i32() ; CHECK-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP15]], 4 ; CHECK-NEXT: [[TMP17:%.*]] = sub i32 [[TMP16]], 1 ; CHECK-NEXT: [[TMP18:%.*]] = extractelement [[TMP9]], i32 [[TMP17]] ; CHECK-NEXT: store i64 [[TMP18]], ptr [[TMP14:%.*]], align 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]] ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw [[TMP9]], [[DOTSPLAT]] ; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 100, [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH:%.*]] ; CHECK: scalar.ph: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[N_VEC]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[GEP_INVAR:%.*]] = getelementptr i8, ptr [[TMP14]], i64 0 ; CHECK-NEXT: store i64 [[IV]], ptr [[GEP_INVAR]], align 1 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 100 ; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: exit: ; CHECK-NEXT: ret void ; ; IC2-LABEL: @test_invar_gep( ; IC2-NEXT: entry: ; IC2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() ; IC2-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3 ; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 100, [[TMP1]] ; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; IC2: vector.ph: ; IC2-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() ; IC2-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP2]], 4 ; IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i64 [[TMP11]], i64 0 ; IC2-NEXT: [[TMP21:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer ; IC2-NEXT: [[TMP3:%.*]] = mul i64 [[TMP11]], 2 ; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 100, [[TMP3]] ; IC2-NEXT: [[N_VEC:%.*]] = sub i64 100, [[N_MOD_VF]] ; IC2-NEXT: [[TMP5:%.*]] = call @llvm.stepvector.nxv4i64() ; IC2-NEXT: [[TMP12:%.*]] = mul nsw [[TMP5]], splat (i64 1) ; IC2-NEXT: [[INDUCTION:%.*]] = add nsw zeroinitializer, [[TMP12]] ; IC2-NEXT: br label [[VECTOR_BODY:%.*]] ; IC2: vector.body: ; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; IC2-NEXT: [[DOTSPLAT:%.*]] = phi [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; IC2-NEXT: [[TMP22:%.*]] = add [[DOTSPLAT]], [[TMP21]] ; IC2-NEXT: [[TMP6:%.*]] = call i32 @llvm.vscale.i32() ; IC2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 4 ; IC2-NEXT: [[TMP8:%.*]] = sub i32 [[TMP7]], 1 ; IC2-NEXT: [[TMP9:%.*]] = extractelement [[TMP22]], i32 [[TMP8]] ; IC2-NEXT: store i64 [[TMP9]], ptr [[DST:%.*]], align 1 ; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]] ; IC2-NEXT: [[VEC_IND_NEXT]] = add nsw [[TMP22]], [[TMP21]] ; IC2-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; IC2-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; IC2: middle.block: ; IC2-NEXT: [[CMP_N:%.*]] = icmp eq i64 100, [[N_VEC]] ; IC2-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] ; IC2: scalar.ph: ; IC2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] ; IC2-NEXT: br label [[LOOP:%.*]] ; IC2: loop: ; IC2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] ; IC2-NEXT: [[GEP_INVAR:%.*]] = getelementptr i8, ptr [[DST]], i64 0 ; IC2-NEXT: store i64 [[IV]], ptr [[GEP_INVAR]], align 1 ; IC2-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; IC2-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 100 ; IC2-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP4:![0-9]+]] ; IC2: exit: ; IC2-NEXT: ret void ; entry: br label %loop loop: %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] %gep.invar = getelementptr i8, ptr %dst, i64 0 store i64 %iv, ptr %gep.invar, align 1 %iv.next = add nsw i64 %iv, 1 %ec = icmp eq i64 %iv.next, 100 br i1 %ec, label %exit, label %loop, !llvm.loop !0 exit: ret void } define void @test_invar_gep_var_start(i64 %start, ptr %dst) #0 { ; CHECK-LABEL: @test_invar_gep_var_start( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 100, [[START:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i64 [[TMP1]], 2 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]] ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP4]] ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] ; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[START]], [[N_VEC]] ; CHECK-NEXT: [[TMP6:%.*]] = call @llvm.stepvector.nxv4i64() ; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[START]], i64 0 ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer ; CHECK-NEXT: [[TMP13:%.*]] = mul nsw [[TMP6]], splat (i64 1) ; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw [[DOTSPLAT]], [[TMP13]] ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement poison, i64 [[TMP4]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector [[BROADCAST_SPLATINSERT1]], poison, zeroinitializer ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP7:%.*]] = phi [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vscale.i32() ; CHECK-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 ; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP9]], 1 ; CHECK-NEXT: [[TMP11:%.*]] = extractelement [[TMP7]], i32 [[TMP10]] ; CHECK-NEXT: store i64 [[TMP11]], ptr [[DST:%.*]], align 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP4]] ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw [[TMP7]], [[BROADCAST_SPLAT2]] ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP5]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY:%.*]] ] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[GEP_INVAR:%.*]] = getelementptr i8, ptr [[DST]], i64 0 ; CHECK-NEXT: store i64 [[IV]], ptr [[GEP_INVAR]], align 1 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 100 ; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP6:![0-9]+]] ; CHECK: exit: ; CHECK-NEXT: ret void ; ; IC2-LABEL: @test_invar_gep_var_start( ; IC2-NEXT: entry: ; IC2-NEXT: [[TMP0:%.*]] = sub i64 100, [[START:%.*]] ; IC2-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() ; IC2-NEXT: [[TMP2:%.*]] = shl nuw nsw i64 [[TMP1]], 3 ; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]] ; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; IC2: vector.ph: ; IC2-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() ; IC2-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 4 ; IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i64 [[TMP4]], i64 0 ; IC2-NEXT: [[TMP9:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer ; IC2-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2 ; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP5]] ; IC2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] ; IC2-NEXT: [[TMP6:%.*]] = add i64 [[START]], [[N_VEC]] ; IC2-NEXT: [[BROADCAST_SPLAT:%.*]] = call @llvm.stepvector.nxv4i64() ; IC2-NEXT: [[DOTSPLATINSERT1:%.*]] = insertelement poison, i64 [[START]], i64 0 ; IC2-NEXT: [[VEC_IND:%.*]] = shufflevector [[DOTSPLATINSERT1]], poison, zeroinitializer ; IC2-NEXT: [[TMP8:%.*]] = mul nsw [[BROADCAST_SPLAT]], splat (i64 1) ; IC2-NEXT: [[INDUCTION:%.*]] = add nsw [[VEC_IND]], [[TMP8]] ; IC2-NEXT: br label [[VECTOR_BODY:%.*]] ; IC2: vector.body: ; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; IC2-NEXT: [[DOTSPLAT:%.*]] = phi [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; IC2-NEXT: [[TMP10:%.*]] = add [[DOTSPLAT]], [[TMP9]] ; IC2-NEXT: [[TMP12:%.*]] = call i32 @llvm.vscale.i32() ; IC2-NEXT: [[TMP13:%.*]] = mul nuw i32 [[TMP12]], 4 ; IC2-NEXT: [[TMP14:%.*]] = sub i32 [[TMP13]], 1 ; IC2-NEXT: [[TMP15:%.*]] = extractelement [[TMP10]], i32 [[TMP14]] ; IC2-NEXT: store i64 [[TMP15]], ptr [[DST:%.*]], align 1 ; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] ; IC2-NEXT: [[VEC_IND_NEXT]] = add nsw [[TMP10]], [[TMP9]] ; IC2-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; IC2-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] ; IC2: middle.block: ; IC2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] ; IC2-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] ; IC2: scalar.ph: ; IC2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP6]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY:%.*]] ] ; IC2-NEXT: br label [[LOOP:%.*]] ; IC2: loop: ; IC2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] ; IC2-NEXT: [[GEP_INVAR:%.*]] = getelementptr i8, ptr [[DST]], i64 0 ; IC2-NEXT: store i64 [[IV]], ptr [[GEP_INVAR]], align 1 ; IC2-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; IC2-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 100 ; IC2-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP6:![0-9]+]] ; IC2: exit: ; IC2-NEXT: ret void ; entry: br label %loop loop: %iv = phi i64 [ %start, %entry ], [ %iv.next, %loop ] %gep.invar = getelementptr i8, ptr %dst, i64 0 store i64 %iv, ptr %gep.invar, align 1 %iv.next = add nsw i64 %iv, 1 %ec = icmp eq i64 %iv.next, 100 br i1 %ec, label %exit, label %loop, !llvm.loop !0 exit: ret void } define void @test_invar_gep_var_start_step_2(i64 %start, ptr %dst) #0 { ; CHECK-LABEL: @test_invar_gep_var_start_step_2( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 98, [[START:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = add nuw i64 [[TMP1]], 1 ; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP4:%.*]] = shl nuw nsw i64 [[TMP3]], 2 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], [[TMP4]] ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 4 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], [[TMP6]] ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] ; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[N_VEC]], 2 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[START]], [[TMP9]] ; CHECK-NEXT: [[TMP10:%.*]] = call @llvm.stepvector.nxv4i64() ; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[START]], i64 0 ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer ; CHECK-NEXT: [[TMP18:%.*]] = mul nsw [[TMP10]], splat (i64 2) ; CHECK-NEXT: [[INDUCTION:%.*]] = add nsw [[DOTSPLAT]], [[TMP18]] ; CHECK-NEXT: [[TMP11:%.*]] = mul nsw i64 2, [[TMP6]] ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement poison, i64 [[TMP11]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector [[BROADCAST_SPLATINSERT1]], poison, zeroinitializer ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP12:%.*]] = phi [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vscale.i32() ; CHECK-NEXT: [[TMP14:%.*]] = mul nuw i32 [[TMP13]], 4 ; CHECK-NEXT: [[TMP15:%.*]] = sub i32 [[TMP14]], 1 ; CHECK-NEXT: [[TMP16:%.*]] = extractelement [[TMP12]], i32 [[TMP15]] ; CHECK-NEXT: store i64 [[TMP16]], ptr [[DST:%.*]], align 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP6]] ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw [[TMP12]], [[BROADCAST_SPLAT2]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[OFFSET_IDX]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY:%.*]] ] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[GEP_INVAR:%.*]] = getelementptr i8, ptr [[DST]], i64 0 ; CHECK-NEXT: store i64 [[IV]], ptr [[GEP_INVAR]], align 1 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 2 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 100 ; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK: exit: ; CHECK-NEXT: ret void ; ; IC2-LABEL: @test_invar_gep_var_start_step_2( ; IC2-NEXT: entry: ; IC2-NEXT: [[TMP0:%.*]] = sub i64 98, [[START:%.*]] ; IC2-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 1 ; IC2-NEXT: [[TMP2:%.*]] = add nuw i64 [[TMP1]], 1 ; IC2-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() ; IC2-NEXT: [[TMP4:%.*]] = shl nuw nsw i64 [[TMP3]], 3 ; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], [[TMP4]] ; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; IC2: vector.ph: ; IC2-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() ; IC2-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 4 ; IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i64 [[TMP6]], i64 0 ; IC2-NEXT: [[BROADCAST_SPLAT1:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer ; IC2-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 2 ; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], [[TMP7]] ; IC2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] ; IC2-NEXT: [[TMP10:%.*]] = mul i64 [[N_VEC]], 2 ; IC2-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[START]], [[TMP10]] ; IC2-NEXT: [[TMP13:%.*]] = mul [[BROADCAST_SPLAT1]], splat (i64 2) ; IC2-NEXT: [[TMP11:%.*]] = call @llvm.stepvector.nxv4i64() ; IC2-NEXT: [[DOTSPLATINSERT1:%.*]] = insertelement poison, i64 [[START]], i64 0 ; IC2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[DOTSPLATINSERT1]], poison, zeroinitializer ; IC2-NEXT: [[TMP12:%.*]] = mul nsw [[TMP11]], splat (i64 2) ; IC2-NEXT: [[INDUCTION:%.*]] = add nsw [[BROADCAST_SPLAT]], [[TMP12]] ; IC2-NEXT: br label [[VECTOR_BODY:%.*]] ; IC2: vector.body: ; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; IC2-NEXT: [[DOTSPLAT:%.*]] = phi [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; IC2-NEXT: [[TMP14:%.*]] = add [[DOTSPLAT]], [[TMP13]] ; IC2-NEXT: [[TMP17:%.*]] = call i32 @llvm.vscale.i32() ; IC2-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 4 ; IC2-NEXT: [[TMP19:%.*]] = sub i32 [[TMP18]], 1 ; IC2-NEXT: [[TMP20:%.*]] = extractelement [[TMP14]], i32 [[TMP19]] ; IC2-NEXT: store i64 [[TMP20]], ptr [[DST:%.*]], align 1 ; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP7]] ; IC2-NEXT: [[VEC_IND_NEXT]] = add nsw [[TMP14]], [[TMP13]] ; IC2-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; IC2-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; IC2: middle.block: ; IC2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] ; IC2-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] ; IC2: scalar.ph: ; IC2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[OFFSET_IDX]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY:%.*]] ] ; IC2-NEXT: br label [[LOOP:%.*]] ; IC2: loop: ; IC2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] ; IC2-NEXT: [[GEP_INVAR:%.*]] = getelementptr i8, ptr [[DST]], i64 0 ; IC2-NEXT: store i64 [[IV]], ptr [[GEP_INVAR]], align 1 ; IC2-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 2 ; IC2-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 100 ; IC2-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP8:![0-9]+]] ; IC2: exit: ; IC2-NEXT: ret void ; entry: br label %loop loop: %iv = phi i64 [ %start, %entry ], [ %iv.next, %loop ] %gep.invar = getelementptr i8, ptr %dst, i64 0 store i64 %iv, ptr %gep.invar, align 1 %iv.next = add nsw i64 %iv, 2 %ec = icmp eq i64 %iv.next, 100 br i1 %ec, label %exit, label %loop, !llvm.loop !0 exit: ret void } define void @test_loop2(i64 %n, ptr %dst) { ; CHECK-LABEL: @test_loop2( ; CHECK-NEXT: iter.check: ; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] ; CHECK: vector.main.loop.iter.check: ; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 ; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 ; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 ; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 ; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 ; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 ; CHECK-NEXT: [[TMP16:%.*]] = sub nsw i64 [[N:%.*]], [[TMP0]] ; CHECK-NEXT: [[TMP17:%.*]] = sub nsw i64 [[N]], [[TMP1]] ; CHECK-NEXT: [[TMP18:%.*]] = sub nsw i64 [[N]], [[TMP2]] ; CHECK-NEXT: [[TMP19:%.*]] = sub nsw i64 [[N]], [[TMP3]] ; CHECK-NEXT: [[TMP20:%.*]] = sub nsw i64 [[N]], [[TMP4]] ; CHECK-NEXT: [[TMP21:%.*]] = sub nsw i64 [[N]], [[TMP5]] ; CHECK-NEXT: [[TMP22:%.*]] = sub nsw i64 [[N]], [[TMP6]] ; CHECK-NEXT: [[TMP23:%.*]] = sub nsw i64 [[N]], [[TMP7]] ; CHECK-NEXT: [[TMP24:%.*]] = sub nsw i64 [[N]], [[TMP8]] ; CHECK-NEXT: [[TMP25:%.*]] = sub nsw i64 [[N]], [[TMP9]] ; CHECK-NEXT: [[TMP26:%.*]] = sub nsw i64 [[N]], [[TMP10]] ; CHECK-NEXT: [[TMP27:%.*]] = sub nsw i64 [[N]], [[TMP11]] ; CHECK-NEXT: [[TMP28:%.*]] = sub nsw i64 [[N]], [[TMP12]] ; CHECK-NEXT: [[TMP29:%.*]] = sub nsw i64 [[N]], [[TMP13]] ; CHECK-NEXT: [[TMP30:%.*]] = sub nsw i64 [[N]], [[TMP14]] ; CHECK-NEXT: [[TMP31:%.*]] = sub nsw i64 [[N]], [[TMP15]] ; CHECK-NEXT: [[TMP32:%.*]] = insertelement <16 x i64> poison, i64 [[TMP16]], i32 0 ; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i64> [[TMP32]], i64 [[TMP17]], i32 1 ; CHECK-NEXT: [[TMP34:%.*]] = insertelement <16 x i64> [[TMP33]], i64 [[TMP18]], i32 2 ; CHECK-NEXT: [[TMP35:%.*]] = insertelement <16 x i64> [[TMP34]], i64 [[TMP19]], i32 3 ; CHECK-NEXT: [[TMP36:%.*]] = insertelement <16 x i64> [[TMP35]], i64 [[TMP20]], i32 4 ; CHECK-NEXT: [[TMP37:%.*]] = insertelement <16 x i64> [[TMP36]], i64 [[TMP21]], i32 5 ; CHECK-NEXT: [[TMP38:%.*]] = insertelement <16 x i64> [[TMP37]], i64 [[TMP22]], i32 6 ; CHECK-NEXT: [[TMP39:%.*]] = insertelement <16 x i64> [[TMP38]], i64 [[TMP23]], i32 7 ; CHECK-NEXT: [[TMP40:%.*]] = insertelement <16 x i64> [[TMP39]], i64 [[TMP24]], i32 8 ; CHECK-NEXT: [[TMP41:%.*]] = insertelement <16 x i64> [[TMP40]], i64 [[TMP25]], i32 9 ; CHECK-NEXT: [[TMP42:%.*]] = insertelement <16 x i64> [[TMP41]], i64 [[TMP26]], i32 10 ; CHECK-NEXT: [[TMP43:%.*]] = insertelement <16 x i64> [[TMP42]], i64 [[TMP27]], i32 11 ; CHECK-NEXT: [[TMP44:%.*]] = insertelement <16 x i64> [[TMP43]], i64 [[TMP28]], i32 12 ; CHECK-NEXT: [[TMP45:%.*]] = insertelement <16 x i64> [[TMP44]], i64 [[TMP29]], i32 13 ; CHECK-NEXT: [[TMP46:%.*]] = insertelement <16 x i64> [[TMP45]], i64 [[TMP30]], i32 14 ; CHECK-NEXT: [[TMP47:%.*]] = insertelement <16 x i64> [[TMP46]], i64 [[TMP31]], i32 15 ; CHECK-NEXT: [[TMP48:%.*]] = trunc <16 x i64> [[TMP47]] to <16 x i8> ; CHECK-NEXT: [[TMP49:%.*]] = add i64 [[TMP0]], [[TMP16]] ; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[DST:%.*]], i64 [[TMP49]] ; CHECK-NEXT: [[TMP51:%.*]] = extractelement <16 x i8> [[TMP48]], i32 15 ; CHECK-NEXT: store i8 [[TMP51]], ptr [[TMP50]], align 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-NEXT: [[TMP52:%.*]] = icmp eq i64 [[INDEX_NEXT]], 992 ; CHECK-NEXT: br i1 [[TMP52]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] ; CHECK: vec.epilog.iter.check: ; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF10:![0-9]+]] ; CHECK: vec.epilog.ph: ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 992, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] ; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] ; CHECK: vec.epilog.vector.body: ; CHECK-NEXT: [[INDEX2:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP53:%.*]] = add i64 [[INDEX2]], 0 ; CHECK-NEXT: [[TMP54:%.*]] = add i64 [[INDEX2]], 1 ; CHECK-NEXT: [[TMP55:%.*]] = add i64 [[INDEX2]], 2 ; CHECK-NEXT: [[TMP56:%.*]] = add i64 [[INDEX2]], 3 ; CHECK-NEXT: [[TMP57:%.*]] = add i64 [[INDEX2]], 4 ; CHECK-NEXT: [[TMP58:%.*]] = add i64 [[INDEX2]], 5 ; CHECK-NEXT: [[TMP59:%.*]] = add i64 [[INDEX2]], 6 ; CHECK-NEXT: [[TMP60:%.*]] = add i64 [[INDEX2]], 7 ; CHECK-NEXT: [[TMP61:%.*]] = sub nsw i64 [[N]], [[TMP53]] ; CHECK-NEXT: [[TMP62:%.*]] = sub nsw i64 [[N]], [[TMP54]] ; CHECK-NEXT: [[TMP63:%.*]] = sub nsw i64 [[N]], [[TMP55]] ; CHECK-NEXT: [[TMP64:%.*]] = sub nsw i64 [[N]], [[TMP56]] ; CHECK-NEXT: [[TMP65:%.*]] = sub nsw i64 [[N]], [[TMP57]] ; CHECK-NEXT: [[TMP66:%.*]] = sub nsw i64 [[N]], [[TMP58]] ; CHECK-NEXT: [[TMP67:%.*]] = sub nsw i64 [[N]], [[TMP59]] ; CHECK-NEXT: [[TMP68:%.*]] = sub nsw i64 [[N]], [[TMP60]] ; CHECK-NEXT: [[TMP69:%.*]] = insertelement <8 x i64> poison, i64 [[TMP61]], i32 0 ; CHECK-NEXT: [[TMP70:%.*]] = insertelement <8 x i64> [[TMP69]], i64 [[TMP62]], i32 1 ; CHECK-NEXT: [[TMP71:%.*]] = insertelement <8 x i64> [[TMP70]], i64 [[TMP63]], i32 2 ; CHECK-NEXT: [[TMP72:%.*]] = insertelement <8 x i64> [[TMP71]], i64 [[TMP64]], i32 3 ; CHECK-NEXT: [[TMP73:%.*]] = insertelement <8 x i64> [[TMP72]], i64 [[TMP65]], i32 4 ; CHECK-NEXT: [[TMP74:%.*]] = insertelement <8 x i64> [[TMP73]], i64 [[TMP66]], i32 5 ; CHECK-NEXT: [[TMP75:%.*]] = insertelement <8 x i64> [[TMP74]], i64 [[TMP67]], i32 6 ; CHECK-NEXT: [[TMP76:%.*]] = insertelement <8 x i64> [[TMP75]], i64 [[TMP68]], i32 7 ; CHECK-NEXT: [[TMP77:%.*]] = trunc <8 x i64> [[TMP76]] to <8 x i8> ; CHECK-NEXT: [[TMP78:%.*]] = add i64 [[TMP53]], [[TMP61]] ; CHECK-NEXT: [[TMP79:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP78]] ; CHECK-NEXT: [[TMP80:%.*]] = extractelement <8 x i8> [[TMP77]], i32 7 ; CHECK-NEXT: store i8 [[TMP80]], ptr [[TMP79]], align 1 ; CHECK-NEXT: [[INDEX_NEXT3]] = add nuw i64 [[INDEX2]], 8 ; CHECK-NEXT: [[TMP81:%.*]] = icmp eq i64 [[INDEX_NEXT3]], 1000 ; CHECK-NEXT: br i1 [[TMP81]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; CHECK: vec.epilog.middle.block: ; CHECK-NEXT: br i1 false, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] ; CHECK: vec.epilog.scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 992, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[SUB_N:%.*]] = sub nsw i64 [[N]], [[IV]] ; CHECK-NEXT: [[SUB_N_TRUNC:%.*]] = trunc i64 [[SUB_N]] to i8 ; CHECK-NEXT: [[ADD:%.*]] = add i64 [[IV]], [[SUB_N]] ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[ADD]] ; CHECK-NEXT: store i8 [[SUB_N_TRUNC]], ptr [[GEP]], align 1 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; CHECK-NEXT: [[C:%.*]] = icmp sle i64 [[IV_NEXT]], 1000 ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP12:![0-9]+]] ; CHECK: exit: ; CHECK-NEXT: ret void ; ; IC2-LABEL: @test_loop2( ; IC2-NEXT: iter.check: ; IC2-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] ; IC2: vector.main.loop.iter.check: ; IC2-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] ; IC2: vector.ph: ; IC2-NEXT: br label [[VECTOR_BODY:%.*]] ; IC2: vector.body: ; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; IC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; IC2-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 ; IC2-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 ; IC2-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 ; IC2-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 ; IC2-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 5 ; IC2-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 6 ; IC2-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 7 ; IC2-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 8 ; IC2-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 9 ; IC2-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 10 ; IC2-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 11 ; IC2-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 12 ; IC2-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 13 ; IC2-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 14 ; IC2-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 15 ; IC2-NEXT: [[TMP16:%.*]] = add i64 [[INDEX]], 16 ; IC2-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 17 ; IC2-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], 18 ; IC2-NEXT: [[TMP19:%.*]] = add i64 [[INDEX]], 19 ; IC2-NEXT: [[TMP20:%.*]] = add i64 [[INDEX]], 20 ; IC2-NEXT: [[TMP21:%.*]] = add i64 [[INDEX]], 21 ; IC2-NEXT: [[TMP22:%.*]] = add i64 [[INDEX]], 22 ; IC2-NEXT: [[TMP23:%.*]] = add i64 [[INDEX]], 23 ; IC2-NEXT: [[TMP24:%.*]] = add i64 [[INDEX]], 24 ; IC2-NEXT: [[TMP25:%.*]] = add i64 [[INDEX]], 25 ; IC2-NEXT: [[TMP26:%.*]] = add i64 [[INDEX]], 26 ; IC2-NEXT: [[TMP27:%.*]] = add i64 [[INDEX]], 27 ; IC2-NEXT: [[TMP28:%.*]] = add i64 [[INDEX]], 28 ; IC2-NEXT: [[TMP29:%.*]] = add i64 [[INDEX]], 29 ; IC2-NEXT: [[TMP30:%.*]] = add i64 [[INDEX]], 30 ; IC2-NEXT: [[TMP31:%.*]] = add i64 [[INDEX]], 31 ; IC2-NEXT: [[TMP32:%.*]] = sub nsw i64 [[N:%.*]], [[TMP0]] ; IC2-NEXT: [[TMP33:%.*]] = sub nsw i64 [[N]], [[TMP1]] ; IC2-NEXT: [[TMP34:%.*]] = sub nsw i64 [[N]], [[TMP2]] ; IC2-NEXT: [[TMP35:%.*]] = sub nsw i64 [[N]], [[TMP3]] ; IC2-NEXT: [[TMP36:%.*]] = sub nsw i64 [[N]], [[TMP4]] ; IC2-NEXT: [[TMP37:%.*]] = sub nsw i64 [[N]], [[TMP5]] ; IC2-NEXT: [[TMP38:%.*]] = sub nsw i64 [[N]], [[TMP6]] ; IC2-NEXT: [[TMP39:%.*]] = sub nsw i64 [[N]], [[TMP7]] ; IC2-NEXT: [[TMP40:%.*]] = sub nsw i64 [[N]], [[TMP8]] ; IC2-NEXT: [[TMP41:%.*]] = sub nsw i64 [[N]], [[TMP9]] ; IC2-NEXT: [[TMP42:%.*]] = sub nsw i64 [[N]], [[TMP10]] ; IC2-NEXT: [[TMP43:%.*]] = sub nsw i64 [[N]], [[TMP11]] ; IC2-NEXT: [[TMP44:%.*]] = sub nsw i64 [[N]], [[TMP12]] ; IC2-NEXT: [[TMP45:%.*]] = sub nsw i64 [[N]], [[TMP13]] ; IC2-NEXT: [[TMP46:%.*]] = sub nsw i64 [[N]], [[TMP14]] ; IC2-NEXT: [[TMP47:%.*]] = sub nsw i64 [[N]], [[TMP15]] ; IC2-NEXT: [[TMP48:%.*]] = insertelement <16 x i64> poison, i64 [[TMP32]], i32 0 ; IC2-NEXT: [[TMP49:%.*]] = insertelement <16 x i64> [[TMP48]], i64 [[TMP33]], i32 1 ; IC2-NEXT: [[TMP50:%.*]] = insertelement <16 x i64> [[TMP49]], i64 [[TMP34]], i32 2 ; IC2-NEXT: [[TMP51:%.*]] = insertelement <16 x i64> [[TMP50]], i64 [[TMP35]], i32 3 ; IC2-NEXT: [[TMP52:%.*]] = insertelement <16 x i64> [[TMP51]], i64 [[TMP36]], i32 4 ; IC2-NEXT: [[TMP53:%.*]] = insertelement <16 x i64> [[TMP52]], i64 [[TMP37]], i32 5 ; IC2-NEXT: [[TMP54:%.*]] = insertelement <16 x i64> [[TMP53]], i64 [[TMP38]], i32 6 ; IC2-NEXT: [[TMP55:%.*]] = insertelement <16 x i64> [[TMP54]], i64 [[TMP39]], i32 7 ; IC2-NEXT: [[TMP56:%.*]] = insertelement <16 x i64> [[TMP55]], i64 [[TMP40]], i32 8 ; IC2-NEXT: [[TMP57:%.*]] = insertelement <16 x i64> [[TMP56]], i64 [[TMP41]], i32 9 ; IC2-NEXT: [[TMP58:%.*]] = insertelement <16 x i64> [[TMP57]], i64 [[TMP42]], i32 10 ; IC2-NEXT: [[TMP59:%.*]] = insertelement <16 x i64> [[TMP58]], i64 [[TMP43]], i32 11 ; IC2-NEXT: [[TMP60:%.*]] = insertelement <16 x i64> [[TMP59]], i64 [[TMP44]], i32 12 ; IC2-NEXT: [[TMP61:%.*]] = insertelement <16 x i64> [[TMP60]], i64 [[TMP45]], i32 13 ; IC2-NEXT: [[TMP62:%.*]] = insertelement <16 x i64> [[TMP61]], i64 [[TMP46]], i32 14 ; IC2-NEXT: [[TMP63:%.*]] = insertelement <16 x i64> [[TMP62]], i64 [[TMP47]], i32 15 ; IC2-NEXT: [[TMP64:%.*]] = sub nsw i64 [[N]], [[TMP16]] ; IC2-NEXT: [[TMP65:%.*]] = sub nsw i64 [[N]], [[TMP17]] ; IC2-NEXT: [[TMP66:%.*]] = sub nsw i64 [[N]], [[TMP18]] ; IC2-NEXT: [[TMP67:%.*]] = sub nsw i64 [[N]], [[TMP19]] ; IC2-NEXT: [[TMP68:%.*]] = sub nsw i64 [[N]], [[TMP20]] ; IC2-NEXT: [[TMP69:%.*]] = sub nsw i64 [[N]], [[TMP21]] ; IC2-NEXT: [[TMP70:%.*]] = sub nsw i64 [[N]], [[TMP22]] ; IC2-NEXT: [[TMP71:%.*]] = sub nsw i64 [[N]], [[TMP23]] ; IC2-NEXT: [[TMP72:%.*]] = sub nsw i64 [[N]], [[TMP24]] ; IC2-NEXT: [[TMP73:%.*]] = sub nsw i64 [[N]], [[TMP25]] ; IC2-NEXT: [[TMP74:%.*]] = sub nsw i64 [[N]], [[TMP26]] ; IC2-NEXT: [[TMP75:%.*]] = sub nsw i64 [[N]], [[TMP27]] ; IC2-NEXT: [[TMP76:%.*]] = sub nsw i64 [[N]], [[TMP28]] ; IC2-NEXT: [[TMP77:%.*]] = sub nsw i64 [[N]], [[TMP29]] ; IC2-NEXT: [[TMP78:%.*]] = sub nsw i64 [[N]], [[TMP30]] ; IC2-NEXT: [[TMP79:%.*]] = sub nsw i64 [[N]], [[TMP31]] ; IC2-NEXT: [[TMP80:%.*]] = insertelement <16 x i64> poison, i64 [[TMP64]], i32 0 ; IC2-NEXT: [[TMP81:%.*]] = insertelement <16 x i64> [[TMP80]], i64 [[TMP65]], i32 1 ; IC2-NEXT: [[TMP82:%.*]] = insertelement <16 x i64> [[TMP81]], i64 [[TMP66]], i32 2 ; IC2-NEXT: [[TMP83:%.*]] = insertelement <16 x i64> [[TMP82]], i64 [[TMP67]], i32 3 ; IC2-NEXT: [[TMP84:%.*]] = insertelement <16 x i64> [[TMP83]], i64 [[TMP68]], i32 4 ; IC2-NEXT: [[TMP85:%.*]] = insertelement <16 x i64> [[TMP84]], i64 [[TMP69]], i32 5 ; IC2-NEXT: [[TMP86:%.*]] = insertelement <16 x i64> [[TMP85]], i64 [[TMP70]], i32 6 ; IC2-NEXT: [[TMP87:%.*]] = insertelement <16 x i64> [[TMP86]], i64 [[TMP71]], i32 7 ; IC2-NEXT: [[TMP88:%.*]] = insertelement <16 x i64> [[TMP87]], i64 [[TMP72]], i32 8 ; IC2-NEXT: [[TMP89:%.*]] = insertelement <16 x i64> [[TMP88]], i64 [[TMP73]], i32 9 ; IC2-NEXT: [[TMP90:%.*]] = insertelement <16 x i64> [[TMP89]], i64 [[TMP74]], i32 10 ; IC2-NEXT: [[TMP91:%.*]] = insertelement <16 x i64> [[TMP90]], i64 [[TMP75]], i32 11 ; IC2-NEXT: [[TMP92:%.*]] = insertelement <16 x i64> [[TMP91]], i64 [[TMP76]], i32 12 ; IC2-NEXT: [[TMP93:%.*]] = insertelement <16 x i64> [[TMP92]], i64 [[TMP77]], i32 13 ; IC2-NEXT: [[TMP94:%.*]] = insertelement <16 x i64> [[TMP93]], i64 [[TMP78]], i32 14 ; IC2-NEXT: [[TMP95:%.*]] = insertelement <16 x i64> [[TMP94]], i64 [[TMP79]], i32 15 ; IC2-NEXT: [[TMP96:%.*]] = trunc <16 x i64> [[TMP63]] to <16 x i8> ; IC2-NEXT: [[TMP97:%.*]] = trunc <16 x i64> [[TMP95]] to <16 x i8> ; IC2-NEXT: [[TMP98:%.*]] = add i64 [[TMP0]], [[TMP32]] ; IC2-NEXT: [[TMP99:%.*]] = add i64 [[TMP16]], [[TMP64]] ; IC2-NEXT: [[TMP100:%.*]] = getelementptr i8, ptr [[DST:%.*]], i64 [[TMP98]] ; IC2-NEXT: [[TMP101:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP99]] ; IC2-NEXT: [[TMP102:%.*]] = extractelement <16 x i8> [[TMP96]], i32 15 ; IC2-NEXT: [[TMP103:%.*]] = extractelement <16 x i8> [[TMP97]], i32 15 ; IC2-NEXT: store i8 [[TMP102]], ptr [[TMP100]], align 1 ; IC2-NEXT: store i8 [[TMP103]], ptr [[TMP101]], align 1 ; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 ; IC2-NEXT: [[TMP104:%.*]] = icmp eq i64 [[INDEX_NEXT]], 992 ; IC2-NEXT: br i1 [[TMP104]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] ; IC2: middle.block: ; IC2-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] ; IC2: vec.epilog.iter.check: ; IC2-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF10:![0-9]+]] ; IC2: vec.epilog.ph: ; IC2-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 992, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] ; IC2-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] ; IC2: vec.epilog.vector.body: ; IC2-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] ; IC2-NEXT: [[TMP105:%.*]] = add i64 [[INDEX1]], 0 ; IC2-NEXT: [[TMP106:%.*]] = add i64 [[INDEX1]], 1 ; IC2-NEXT: [[TMP107:%.*]] = add i64 [[INDEX1]], 2 ; IC2-NEXT: [[TMP108:%.*]] = add i64 [[INDEX1]], 3 ; IC2-NEXT: [[TMP109:%.*]] = add i64 [[INDEX1]], 4 ; IC2-NEXT: [[TMP110:%.*]] = add i64 [[INDEX1]], 5 ; IC2-NEXT: [[TMP111:%.*]] = add i64 [[INDEX1]], 6 ; IC2-NEXT: [[TMP112:%.*]] = add i64 [[INDEX1]], 7 ; IC2-NEXT: [[TMP113:%.*]] = sub nsw i64 [[N]], [[TMP105]] ; IC2-NEXT: [[TMP114:%.*]] = sub nsw i64 [[N]], [[TMP106]] ; IC2-NEXT: [[TMP115:%.*]] = sub nsw i64 [[N]], [[TMP107]] ; IC2-NEXT: [[TMP116:%.*]] = sub nsw i64 [[N]], [[TMP108]] ; IC2-NEXT: [[TMP117:%.*]] = sub nsw i64 [[N]], [[TMP109]] ; IC2-NEXT: [[TMP118:%.*]] = sub nsw i64 [[N]], [[TMP110]] ; IC2-NEXT: [[TMP119:%.*]] = sub nsw i64 [[N]], [[TMP111]] ; IC2-NEXT: [[TMP120:%.*]] = sub nsw i64 [[N]], [[TMP112]] ; IC2-NEXT: [[TMP121:%.*]] = insertelement <8 x i64> poison, i64 [[TMP113]], i32 0 ; IC2-NEXT: [[TMP122:%.*]] = insertelement <8 x i64> [[TMP121]], i64 [[TMP114]], i32 1 ; IC2-NEXT: [[TMP123:%.*]] = insertelement <8 x i64> [[TMP122]], i64 [[TMP115]], i32 2 ; IC2-NEXT: [[TMP124:%.*]] = insertelement <8 x i64> [[TMP123]], i64 [[TMP116]], i32 3 ; IC2-NEXT: [[TMP125:%.*]] = insertelement <8 x i64> [[TMP124]], i64 [[TMP117]], i32 4 ; IC2-NEXT: [[TMP126:%.*]] = insertelement <8 x i64> [[TMP125]], i64 [[TMP118]], i32 5 ; IC2-NEXT: [[TMP127:%.*]] = insertelement <8 x i64> [[TMP126]], i64 [[TMP119]], i32 6 ; IC2-NEXT: [[TMP128:%.*]] = insertelement <8 x i64> [[TMP127]], i64 [[TMP120]], i32 7 ; IC2-NEXT: [[TMP129:%.*]] = trunc <8 x i64> [[TMP128]] to <8 x i8> ; IC2-NEXT: [[TMP130:%.*]] = add i64 [[TMP105]], [[TMP113]] ; IC2-NEXT: [[TMP131:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP130]] ; IC2-NEXT: [[TMP132:%.*]] = extractelement <8 x i8> [[TMP129]], i32 7 ; IC2-NEXT: store i8 [[TMP132]], ptr [[TMP131]], align 1 ; IC2-NEXT: [[INDEX_NEXT2]] = add nuw i64 [[INDEX1]], 8 ; IC2-NEXT: [[TMP133:%.*]] = icmp eq i64 [[INDEX_NEXT2]], 1000 ; IC2-NEXT: br i1 [[TMP133]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; IC2: vec.epilog.middle.block: ; IC2-NEXT: br i1 false, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] ; IC2: vec.epilog.scalar.ph: ; IC2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 992, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] ; IC2-NEXT: br label [[LOOP:%.*]] ; IC2: loop: ; IC2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] ; IC2-NEXT: [[SUB_N:%.*]] = sub nsw i64 [[N]], [[IV]] ; IC2-NEXT: [[SUB_N_TRUNC:%.*]] = trunc i64 [[SUB_N]] to i8 ; IC2-NEXT: [[ADD:%.*]] = add i64 [[IV]], [[SUB_N]] ; IC2-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[ADD]] ; IC2-NEXT: store i8 [[SUB_N_TRUNC]], ptr [[GEP]], align 1 ; IC2-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; IC2-NEXT: [[C:%.*]] = icmp sle i64 [[IV_NEXT]], 1000 ; IC2-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP12:![0-9]+]] ; IC2: exit: ; IC2-NEXT: ret void ; entry: br label %loop loop: %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] %sub.n = sub nsw i64 %n, %iv %sub.n.trunc = trunc i64 %sub.n to i8 %add = add i64 %iv, %sub.n %gep = getelementptr i8, ptr %dst, i64 %add store i8 %sub.n.trunc, ptr %gep, align 1 %iv.next = add nsw i64 %iv, 1 %c = icmp sle i64 %iv.next, 1000 br i1 %c, label %loop, label %exit exit: ret void } attributes #0 = { "target-features"="+neon,+sve" vscale_range(1, 16) } !0 = distinct !{!0, !1, !2, !3, !4, !5} !1 = !{!"llvm.loop.mustprogress"} !2 = !{!"llvm.loop.vectorize.width", i32 4} !3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true} !4 = !{!"llvm.loop.vectorize.enable", i1 true} !5 = !{!"llvm.loop.interleave.count", i32 1}