; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s --check-prefix=X86 %}
; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefix=AARCH64 %}


define i1 @test(i32 %0, i32 %1, i32 %p) {
; X86-LABEL: define i1 @test(
; X86-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[P:%.*]]) {
; X86-NEXT:  entry:
; X86-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 0
; X86-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
; X86-NEXT:    [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; X86-NEXT:    [[TMP4:%.*]] = shl <4 x i32> zeroinitializer, [[TMP3]]
; X86-NEXT:    [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer
; X86-NEXT:    [[CMP6:%.*]] = icmp slt i32 0, [[P]]
; X86-NEXT:    [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]]
; X86-NEXT:    [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])
; X86-NEXT:    [[OP_RDX:%.*]] = select i1 [[TMP7]], i1 true, i1 [[CMP6]]
; X86-NEXT:    [[OP_RDX1:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP1]]
; X86-NEXT:    [[TMP8:%.*]] = freeze i1 [[OP_RDX]]
; X86-NEXT:    [[OP_RDX2:%.*]] = select i1 [[TMP8]], i1 true, i1 [[OP_RDX1]]
; X86-NEXT:    ret i1 [[OP_RDX2]]
;
; AARCH64-LABEL: define i1 @test(
; AARCH64-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[P:%.*]]) {
; AARCH64-NEXT:  entry:
; AARCH64-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 0
; AARCH64-NEXT:    [[SHL4:%.*]] = shl i32 0, [[TMP1]]
; AARCH64-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[SHL4]], 0
; AARCH64-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[TMP1]], i32 1
; AARCH64-NEXT:    [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; AARCH64-NEXT:    [[TMP4:%.*]] = shl <4 x i32> zeroinitializer, [[TMP3]]
; AARCH64-NEXT:    [[TMP5:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[P]], i32 0
; AARCH64-NEXT:    [[TMP6:%.*]] = icmp slt <4 x i32> [[TMP4]], [[TMP5]]
; AARCH64-NEXT:    [[TMP7:%.*]] = freeze <4 x i1> [[TMP6]]
; AARCH64-NEXT:    [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])
; AARCH64-NEXT:    [[OP_RDX:%.*]] = select i1 [[TMP8]], i1 true, i1 [[CMP5]]
; AARCH64-NEXT:    [[OP_RDX1:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP1]]
; AARCH64-NEXT:    [[TMP9:%.*]] = freeze i1 [[OP_RDX]]
; AARCH64-NEXT:    [[OP_RDX2:%.*]] = select i1 [[TMP9]], i1 true, i1 [[OP_RDX1]]
; AARCH64-NEXT:    ret i1 [[OP_RDX2]]
;
entry:
  %cmp1 = icmp sgt i32 %0, 0
  %shl1 = shl i32 0, %1
  %cmp2 = icmp slt i32 %shl1, 0
  %2 = select i1 %cmp1, i1 true, i1 %cmp2
  %shl2 = shl i32 0, %1
  %cmp3 = icmp slt i32 %shl2, 0
  %3 = select i1 %2, i1 true, i1 %cmp3
  %shl3 = shl i32 0, %1
  %cmp4 = icmp slt i32 %shl3, 0
  %4 = select i1 %3, i1 true, i1 %cmp4
  %shl4 = shl i32 0, %1
  %cmp5 = icmp slt i32 %shl4, 0
  %5 = select i1 %4, i1 true, i1 %cmp5
  %cmp6 = icmp slt i32 0, %p
  %sel = select i1 %cmp1, i1 true, i1 %cmp6
  %6 = or i1 %sel, %5
  ret i1 %6
}