===STDOUT=== Section "Monitor" Identifier "HP LP2480zx" ModelName "HP LP2480zx" VendorName "HWP" # Monitor Manufactured week 20 of 2008 # EDID version 1.3 # Digital Display DisplaySize 520 320 Gamma 2.20 Option "DPMS" "true" Horizsync 24-80 VertRefresh 47-61 # Maximum pixel clock is 170MHz #Not giving standard mode: 1280x960, 60Hz #Not giving standard mode: 1280x1024, 60Hz #Not giving standard mode: 1600x1000, 60Hz #Not giving standard mode: 1600x1200, 60Hz #Not giving standard mode: 1680x1050, 60Hz #Not giving standard mode: 1920x1080, 60Hz #Not giving standard mode: 1920x1200, 60Hz #Extension block found. Parsing... Modeline "Mode 16" 148.50 1920 2008 2052 2200 1080 1084 1089 1125 +hsync +vsync Modeline "Mode 0" 154.00 1920 1968 2000 2080 1200 1203 1209 1235 +hsync -vsync Modeline "Mode 1" 148.500 1920 2008 2052 2200 1080 1084 1089 1125 +hsync +vsync Modeline "Mode 2" 25.200 640 656 752 800 480 490 492 525 -hsync -vsync Modeline "Mode 3" 27.027 720 736 798 858 480 489 495 525 -hsync -vsync Modeline "Mode 4" 27.027 720 736 798 858 480 489 495 525 -hsync -vsync Modeline "Mode 5" 74.250 1280 1390 1420 1650 720 725 730 750 +hsync +vsync Modeline "Mode 6" 74.250 1920 2008 2052 2200 1080 1082 1087 1125 +hsync +vsync interlace Modeline "Mode 7" 27.027 1440 1478 1602 1716 480 484 487 525 -hsync -vsync interlace Modeline "Mode 8" 27.027 1440 1478 1602 1716 480 484 487 525 -hsync -vsync interlace Modeline "Mode 9" 27.000 720 732 796 864 576 581 586 625 -hsync -vsync Modeline "Mode 10" 27.000 720 732 796 864 576 581 586 625 -hsync -vsync Modeline "Mode 11" 74.250 1280 1720 1760 1980 720 725 730 750 +hsync +vsync Modeline "Mode 12" 74.250 1920 2448 2492 2640 1080 1082 1089 1125 +hsync +vsync interlace Modeline "Mode 13" 27.000 1440 1464 1590 1728 576 578 581 625 -hsync -vsync interlace Modeline "Mode 14" 27.000 1440 1464 1590 1728 576 578 581 625 -hsync -vsync interlace Modeline "Mode 15" 148.500 1920 2448 2492 2640 1080 1084 1089 1125 +hsync +vsync Option "PreferredMode" "Mode 16" EndSection ===STDERR=== Checksum Correct ===RC=== 0