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1What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health2Date: June 20183KernelVersion: 4.194Contact: Vadim Pasternak <vadimp@nvidia.com>5Description: This file shows ASIC health status. The possible values are:6 0 - health failed, 2 - health OK, 3 - ASIC in booting state.7 8 The files are read only.9 10What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version11What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version12Date: June 201813KernelVersion: 4.1914Contact: Vadim Pasternak <vadimp@nvidia.com>15Description: These files show with which CPLD versions have been burned16 on carrier and switch boards.17 18 The files are read only.19 20What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir21Date: December 201822KernelVersion: 5.023Contact: Vadim Pasternak <vadimp@nvidia.com>24Description: This file shows the system fans direction:25 forward direction - relevant bit is set 0;26 reversed direction - relevant bit is set 1.27 28 The files are read only.29 30What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version31Date: November 201832KernelVersion: 5.033Contact: Vadim Pasternak <vadimp@nvidia.com>34Description: These files show with which CPLD versions have been burned35 on LED or Gearbox board.36 37 The files are read only.38 39What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable40Date: November 201841KernelVersion: 5.042Contact: Vadim Pasternak <vadimp@nvidia.com>43Description: These files enable and disable the access to the JTAG domain.44 By default access to the JTAG domain is disabled.45 46 The file is read/write.47 48What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/select_iio49Date: June 201850KernelVersion: 4.1951Contact: Vadim Pasternak <vadimp@nvidia.com>52Description: This file allows iio devices selection.53 54 Attribute select_iio can be written with 0 or with 1. It55 selects which one of iio devices can be accessed.56 57 The file is read/write.58 59What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu1_on60 /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu2_on61 /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_cycle62 /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_down63Date: June 201864KernelVersion: 4.1965Contact: Vadim Pasternak <vadimp@nvidia.com>66Description: These files allow asserting system power cycling, switching67 power supply units on and off and system's main power domain68 shutdown.69 Expected behavior:70 When pwr_cycle is written 1: auxiliary power domain will go71 down and after short period (about 1 second) up.72 When psu1_on or psu2_on is written 1, related unit will be73 disconnected from the power source, when written 0 - connected.74 If both are written 1 - power supplies main power domain will75 go down.76 When pwr_down is written 1, system's main power domain will go77 down.78 79 The files are write only.80 81What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_aux_pwr_or_ref82What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_asic_thermal83What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_hotswap_or_halt84What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_hotswap_or_wd85What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_fw_reset86What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_long_pb87What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_main_pwr_fail88What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_short_pb89What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sw_reset90Date: June 201891KernelVersion: 4.1992Contact: Vadim Pasternak <vadimp@nvidia.com>93Description: These files show the system reset cause, as following: power94 auxiliary outage or power refresh, ASIC thermal shutdown, halt,95 hotswap, watchdog, firmware reset, long press power button,96 short press power button, software reset. Value 1 in file means97 this is reset cause, 0 - otherwise. Only one of the above98 causes could be 1 at the same time, representing only last99 reset cause.100 101 The files are read only.102 103What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_comex_pwr_fail104What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_from_comex105What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_system106What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_voltmon_upgrade_fail107Date: November 2018108KernelVersion: 5.0109Contact: Vadim Pasternak <vadimp@nvidia.com>110Description: These files show the system reset cause, as following: ComEx111 power fail, reset from ComEx, system platform reset, reset112 due to voltage monitor devices upgrade failure,113 Value 1 in file means this is reset cause, 0 - otherwise.114 Only one bit could be 1 at the same time, representing only115 the last reset cause.116 117 The files are read only.118 119What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version120Date: November 2018121KernelVersion: 5.0122Contact: Vadim Pasternak <vadimp@nvidia.com>123Description: These files show with which CPLD versions have been burned124 on LED board.125 126 The files are read only.127 128What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_comex_thermal129What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_comex_wd130What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_from_asic131What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_reload_bios132What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sff_wd133What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_swb_wd134Date: June 2019135KernelVersion: 5.3136Contact: Vadim Pasternak <vadimp@nvidia.com>137Description: These files show the system reset cause, as following:138 COMEX thermal shutdown; wathchdog power off or reset was derived139 by one of the next components: COMEX, switch board or by Small Form140 Factor mezzanine, reset requested from ASIC, reset caused by BIOS141 reload. Value 1 in file means this is reset cause, 0 - otherwise.142 Only one of the above causes could be 1 at the same time, representing143 only last reset cause.144 145 The files are read only.146 147What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config1148What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config2149Date: January 2020150KernelVersion: 5.6151Contact: Vadim Pasternak <vadimp@nvidia.com>152Description: These files show system static topology identification153 like system's static I2C topology, number and type of FPGA154 devices within the system and so on.155 156 The files are read only.157 158What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_ac_pwr_fail159What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_platform160What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_soc161What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_sw_pwr_off162Date: January 2020163KernelVersion: 5.6164Contact: Vadim Pasternak <vadimp@nvidia.com>165Description: These files show the system reset causes, as following: reset166 due to AC power failure, reset invoked from software by167 assertion reset signal through CPLD. reset caused by signal168 asserted by SOC through ACPI register, reset invoked from169 software by assertion power off signal through CPLD.170 171 The files are read only.172 173What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pcie_asic_reset_dis174Date: January 2020175KernelVersion: 5.6176Contact: Vadim Pasternak <vadimp@nvidia.com>177Description: This file allows to retain ASIC up during PCIe root complex178 reset, when attribute is set 1.179 180 The file is read/write.181 182What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/vpd_wp183Date: January 2020184KernelVersion: 5.6185Contact: Vadim Pasternak <vadimp@nvidia.com>186Description: This file allows to overwrite system VPD hardware write187 protection when attribute is set 1.188 189 The file is read/write.190 191What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/voltreg_update_status192Date: January 2020193KernelVersion: 5.6194Contact: Vadim Pasternak <vadimp@nvidia.com>195Description: This file exposes the configuration update status of burnable196 voltage regulator devices. The status values are as following:197 0 - OK; 1 - CRC failure; 2 = I2C failure; 3 - in progress.198 199 The file is read only.200 201What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/ufm_version202Date: January 2020203KernelVersion: 5.6204Contact: Vadim Pasternak <vadimp@nvidia.com>205Description: This file exposes the firmware version of burnable voltage206 regulator devices.207 208 The file is read only.209 210What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_pn211What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_pn212What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_pn213What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_pn214What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version_min215What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version_min216What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version_min217What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version_min218Date: July 2020219KernelVersion: 5.9220Contact: Vadim Pasternak <vadimp@nvidia.com>221Description: These files show with which CPLD part numbers and minor222 versions have been burned CPLD devices equipped on a223 system.224 225 The files are read only.226 227What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_active_image228What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_auth_fail229What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_upgrade_fail230Date: October 2021231KernelVersion: 5.16232Contact: Vadim Pasternak <vadimp@nvidia.com>233Description: The files represent BIOS statuses:234 235 bios_active_image: location of current active BIOS image:236 0: Top, 1: Bottom.237 The reported value should correspond to value expected by OS238 in case of BIOS safe mode is 0. This bit is related to Intel239 top-swap feature of DualBios on the same flash.240 241 bios_auth_fail: BIOS upgrade is failed because provided BIOS242 image is not signed correctly.243 244 bios_upgrade_fail: BIOS upgrade is failed by some other245 reason not because authentication. For example due to246 physical SPI flash problem.247 248 The files are read only.249 250What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_enable251What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_enable252What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_enable253What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_enable254What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_enable255What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_enable256What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_enable257What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_enable258Date: October 2021259KernelVersion: 5.16260Contact: Vadim Pasternak <vadimp@nvidia.com>261Description: These files allow line cards enable state control.262 Expected behavior:263 When lc{n}_enable is written 1, related line card is released264 from the reset state, when 0 - is hold in reset state.265 266 The files are read/write.267 268What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_pwr269What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_pwr270What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_pwr271What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_pwr272What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_pwr273What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_pwr274What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_pwr275What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_pwr276Date: October 2021277KernelVersion: 5.16278Contact: Vadim Pasternak <vadimp@nvidia.com>279Description: These files switching line cards power on and off.280 Expected behavior:281 When lc{n}_pwr is written 1, related line card is powered282 on, when written 0 - powered off.283 284 The files are read/write.285 286What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_rst_mask287What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_rst_mask288What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_rst_mask289What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_rst_mask290What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_rst_mask291What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_rst_mask292What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_rst_mask293What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_rst_mask294Date: October 2021295KernelVersion: 5.16296Contact: Vadim Pasternak <vadimp@nvidia.com>297Description: These files clear line card reset bit enforced by ASIC, when it298 sets it due to some abnormal ASIC behavior.299 Expected behavior:300 When lc{n}_rst_mask is written 1, related line card reset bit301 is cleared, when written 0 - no effect.302 303 The files are write only.304 305What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/os_started306Date: October 2021307KernelVersion: 5.16308Contact: Vadim Pasternak <vadimp@nvidia.com>309Description: This file, when written 1, indicates to programmable devices310 that OS is taking control over it.311 312 The file is read/write.313 314What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pm_mgmt_en315Date: October 2021316KernelVersion: 5.16317Contact: Vadim Pasternak <vadimp@nvidia.com>318Description: This file assigns power management control ownership.319 When power management control is provided by hardware, hardware320 will automatically power off one or more line previously321 powered line cards in case system power budget is getting322 insufficient. It could be in case when some of power units lost323 power good state.324 When pm_mgmt_en is written 1, power management control by325 software is enabled, 0 - power management control by hardware.326 Note that for any setting of pm_mgmt_en attribute hardware will327 not allow to power on any new line card in case system power328 budget is insufficient.329 Same in case software will try to power on several line cards330 at once - hardware will power line cards while system has331 enough power budget.332 Default is 0.333 334 The file is read/write.335 336What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu3_on337What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu4_on338Date: October 2021339KernelVersion: 5.16340Contact: Vadim Pasternak <vadimp@nvidia.com>341Description: These files switching power supply units on and off.342 Expected behavior:343 When psu3_on or psu4_on is written 1, related unit will be344 disconnected from the power source, when written 0 - connected.345 346 The files are write only.347 348What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/shutdown_unlock349Date: October 2021350KernelVersion: 5.16351Contact: Vadim Pasternak <vadimp@nvidia.com>352Description: This file allows to unlock ASIC after thermal shutdown event.353 When system thermal shutdown is enforced by ASIC, ASIC is354 getting locked and after system boot it will not be available.355 Software can decide to unlock it by setting this attribute to356 1 and then perform system power cycle by setting pwr_cycle357 attribute to 1 (power cycle of main power domain).358 Before setting shutdown_unlock to 1 it is recommended to359 validate that system reboot cause is reset_asic_thermal or360 reset_thermal_spc_or_pciesw.361 In case shutdown_unlock is not set 1, the only way to release362 ASIC from locking - is full system power cycle through the363 external power distribution unit.364 Default is 1.365 366 The file is read/write.367 368What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_pn369What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version370What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version_min371Date: October 2021372KernelVersion: 5.16373Contact: Vadim Pasternak <vadimp@nvidia.com>374Description: These files show with which CPLD major and minor versions375 and part number has been burned CPLD device on line card.376 377 The files are read only.378 379What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_pn380What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version381What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version_min382Date: October 2021383KernelVersion: 5.16384Contact: Vadim Pasternak <vadimp@nvidia.com>385Description: These files show with which FPGA major and minor versions386 and part number has been burned FPGA device on line card.387 388 The files are read only.389 390What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/vpd_wp391Date: October 2021392KernelVersion: 5.16393Contact: Vadim Pasternak <vadimp@nvidia.com>394Description: This file allow to overwrite line card VPD hardware write395 protection mode. When attribute is set 1 - write protection is396 disabled, when 0 - enabled.397 Default is 0.398 If the system is in locked-down mode writing this file will not399 be allowed.400 The purpose if this file is to allow line card VPD burning401 during production flow.402 403 The file is read/write.404 405What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_ref406What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_dc_dc_pwr_fail407What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_fpga_not_done408What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_from_chassis409What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_line_card410What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_pwr_off_from_chassis411Date: October 2021412KernelVersion: 5.16413Contact: Vadim Pasternak <vadimp@nvidia.com>414Description: These files show the line reset cause, as following: power415 auxiliary outage or power refresh, DC-to-DC power failure, FPGA reset416 failed, line card reset failed, power off from chassis.417 Value 1 in file means this is reset cause, 0 - otherwise. Only one of418 the above causes could be 1 at the same time, representing only last419 reset cause.420 421 The files are read only.422 423What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld_upgrade_en424What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_upgrade_en425Date: October 2021426KernelVersion: 5.16427Contact: Vadim Pasternak <vadimp@nvidia.com>428Description: These files allow CPLD and FPGA burning. Value 1 in file means burning429 is enabled, 0 - otherwise.430 If the system is in locked-down mode writing these files will431 not be allowed.432 The purpose of these files to allow line card CPLD and FPGA433 upgrade through the JTAG daisy-chain.434 435 The files are read/write.436 437What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/qsfp_pwr_en438What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/pwr_en439Date: October 2021440KernelVersion: 5.16441Contact: Vadim Pasternak <vadimp@nvidia.com>442Description: These files allow to power on/off all QSFP ports and whole line card.443 The attributes are set 1 for power on, 0 - for power off.444 445 The files are read/write.446 447What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/agb_spi_burn_en448What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_spi_burn_en449Date: October 2021450KernelVersion: 5.16451Contact: Vadim Pasternak <vadimp@nvidia.com>452Description: These files allow gearboxes and FPGA SPI flash burning.453 The attributes are set 1 to enable burning, 0 - to disable.454 If the system is in locked-down mode writing these files will455 not be allowed.456 The purpose of these files to allow line card Gearboxes and FPGA457 burning during production flow.458 459 The file is read/write.460 461What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/max_power462What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/config463Date: October 2021464KernelVersion: 5.16465Contact: Vadim Pasternak <vadimp@nvidia.com>466Description: These files provide the maximum powered required for line card467 feeding and line card configuration Id.468 469 The files are read only.470 471What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/phy_reset472Date: May 2022473KernelVersion: 5.19474Contact: Vadim Pasternak <vadimp@nvidia.com>475Description: This file allows to reset PHY 88E1548 when attribute is set 0476 due to some abnormal PHY behavior.477 Expected behavior:478 When phy_reset is written 1, all PHY 88E1548 are released479 from the reset state, when 0 - are hold in reset state.480 481 The files are read/write.482 483What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/mac_reset484Date: May 2022485KernelVersion: 5.19486Contact: Vadim Pasternak <vadimp@nvidia.com>487Description: This file allows to reset ASIC MT52132 when attribute is set 0488 due to some abnormal ASIC behavior.489 Expected behavior:490 When mac_reset is written 1, the ASIC MT52132 is released491 from the reset state, when 0 - is hold in reset state.492 493 The files are read/write.494 495What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/qsfp_pwr_good496Date: May 2022497KernelVersion: 5.19498Contact: Vadim Pasternak <vadimp@nvidia.com>499Description: This file shows QSFP ports power status. The value is set to 0500 when one of any QSFP ports is plugged. The value is set to 1 when501 there are no any QSFP ports are plugged.502 The possible values are:503 0 - Power good, 1 - Not power good.504 505 The files are read only.506 507What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic2_health508Date: July 2022509KernelVersion: 5.20510Contact: Vadim Pasternak <vadimp@nvidia.com>511Description: This file shows 2-nd ASIC health status. The possible values are:512 0 - health failed, 2 - health OK, 3 - ASIC in booting state.513 514 The file is read only.515 516What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_reset517What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic2_reset518Date: July 2022519KernelVersion: 5.20520Contact: Vadim Pasternak <vadimp@nvidia.com>521Description: These files allow to each of ASICs by writing 1.522 523 The files are write only.524 525What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/comm_chnl_ready526Date: July 2022527KernelVersion: 5.20528Contact: Vadim Pasternak <vadimp@nvidia.com>529Description: This file is used to indicate remote end (for example BMC) that system530 host CPU is ready for sending telemetry data to remote end.531 For indication the file should be written 1.532 533 The file is write only.534 535What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/config3536Date: January 2020537KernelVersion: 5.6538Contact: Vadim Pasternak <vadimp@nvidia.com>539Description: The file indicates COME module hardware configuration.540 The value is pushed by hardware through GPIO pins.541 The purpose is to expose some minor BOM changes for the same system SKU.542 543 The file is read only.544 545What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_pwr_converter_fail546Date: February 2023547KernelVersion: 6.3548Contact: Vadim Pasternak <vadimp@nvidia.com>549Description: This file shows the system reset cause due to power converter550 devices failure.551 Value 1 in file means this is reset cause, 0 - otherwise.552 553 The file is read only.554 555What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_ap_reset556What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_ap_reset557Date: February 2023558KernelVersion: 6.3559Contact: Vadim Pasternak <vadimp@nvidia.com>560Description: These files aim to monitor the status of the External Root of Trust (EROT)561 processor's RESET output to the Application Processor (AP).562 By reading this file, could be determined if the EROT has invalidated or563 revoked AP Firmware, at which point it will hold the AP in RESET until a564 valid firmware is loaded. This protects the AP from running an565 unauthorized firmware. In the normal flow, the AP reset should be released566 after the EROT validates the integrity of the FW, and it should be done so567 as quickly as possible so that the AP boots before the CPU starts to568 communicate to each ASIC.569 570 The files are read only.571 572What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_recovery573What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_recovery574What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_reset575What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_reset576Date: February 2023577KernelVersion: 6.3578Contact: Vadim Pasternak <vadimp@nvidia.com>579Description: These files aim to perform External Root of Trust (EROT) recovery580 sequence after EROT device failure.581 These EROT devices protect ASICs from unauthorized access and in normal582 flow their reset should be released with system power – earliest power583 up stage, so that EROTs can begin boot and authentication process before584 CPU starts to communicate to ASICs.585 Issuing a reset to the EROT while asserting the recovery signal will cause586 the EROT Application Processor to enter recovery mode so that the EROT FW587 can be updated/recovered.588 For reset/recovery the related file should be toggled by 1/0.589 590 The files are read/write.591 592What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_wp593What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_wp594Date: February 2023595KernelVersion: 6.3596Contact: Vadim Pasternak <vadimp@nvidia.com>597Description: These files allow access to External Root of Trust (EROT) for reset598 and recovery sequence after EROT device failure.599 Default is 0 (programming disabled).600 If the system is in locked-down mode writing this file will not be allowed.601 602 The files are read/write.603 604What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/spi_chnl_select605Date: February 2023606KernelVersion: 6.3607Contact: Vadim Pasternak <vadimp@nvidia.com>608Description: This file allows SPI chip selection for External Root of Trust (EROT)609 device Out-of-Band recovery.610 File can be written with 0 or with 1. It selects which EROT can be accessed611 through SPI device.612 613 The file is read/write.614 615What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_pg_fail616Date: February 2023617KernelVersion: 6.3618Contact: Vadim Pasternak vadimp@nvidia.com619Description: This file shows ASIC Power Good status.620 Value 1 in file means ASIC Power Good failed, 0 - otherwise.621 622 The file is read only.623 624What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd1_boot_fail625What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd2_boot_fail626What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_fail627Date: February 2023628KernelVersion: 6.3629Contact: Vadim Pasternak vadimp@nvidia.com630Description: These files are related to clock boards status in system.631 - clk_brd1_boot_fail: warning about 1-st clock board failed to boot from CI.632 - clk_brd2_boot_fail: warning about 2-nd clock board failed to boot from CI.633 - clk_brd_fail: error about common clock board boot failure.634 635 The files are read only.636 637What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_prog_en638Date: February 2023639KernelVersion: 6.3640Contact: Vadim Pasternak <vadimp@nvidia.com>641Description: This file enables programming of clock boards.642 Default is 0 (programming disabled).643 If the system is in locked-down mode writing this file will not be allowed.644 645 The file is read/write.646 647What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_converter_prog_en648Date: February 2023649KernelVersion: 6.3650Contact: Vadim Pasternak <vadimp@nvidia.com>651Description: This file enables programming of power converters.652 Default is 0 (programming disabled).653 If the system is in locked-down mode writing this file will not be allowed.654 655 The file is read/write.656 657What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_ac_ok_fail658Date: February 2023659KernelVersion: 6.3660Contact: Vadim Pasternak <vadimp@nvidia.com>661Description: This file shows the system reset cause due to AC power failure.662 Value 1 in file means this is reset cause, 0 - otherwise.663 664 The file is read only.665 666What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_pn667What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version668What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version_min669Date: August 2023670KernelVersion: 6.6671Contact: Vadim Pasternak <vadimp@nvidia.com>672Description: These files show with which CPLD part numbers, version and minor673 versions have been burned the 5-th CPLD device equipped on a674 system.675 676 The files are read only.677 678What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_cap679Date: August 2023680KernelVersion: 6.6681Contact: Vadim Pasternak <vadimp@nvidia.com>682Description: This file indicates the available method of CPLD/FPGA devices683 field update through the JTAG chain:684 685 b00 - field update through LPC bus register memory space.686 b01 - Reserved.687 b10 - Reserved.688 b11 - field update through CPU GPIOs bit-banging.689 690 The file is read only.691 692What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lid_open693Date: August 2023694KernelVersion: 6.6695Contact: Vadim Pasternak <vadimp@nvidia.com>696Description: 1 - indicates that system lid is opened, otherwise 0.697 698 The file is read only.699 700What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_long_pwr_pb701Date: August 2023702KernelVersion: 6.6703Contact: Vadim Pasternak <vadimp@nvidia.com>704Description: This file if set 1 indicates that system has been reset by705 long press of power button.706 707 The file is read only.708 709What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_swb_dc_dc_pwr_fail710Date: August 2023711KernelVersion: 6.6712Contact: Vadim Pasternak <vadimp@nvidia.com>713Description: This file shows 1 in case the system reset happened due to the714 failure of any DC-DC power converter devices equipped on the715 switch board.716 717 The file is read only.718