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1What: /sys/kernel/debug/dcc/.../ready2Date: December 20223Contact: Souradeep Chowdhury <quic_schowdhu@quicinc.com>4Description:5 This file is used to check the status of the dcc6 hardware if it's ready to receive user configurations.7 A 'Y' here indicates dcc is ready.8 9What: /sys/kernel/debug/dcc/.../trigger10Date: December 202211Contact: Souradeep Chowdhury <quic_schowdhu@quicinc.com>12Description:13 This is the debugfs interface for manual software14 triggers. The trigger can be invoked by writing '1'15 to the file.16 17What: /sys/kernel/debug/dcc/.../config_reset18Date: December 202219Contact: Souradeep Chowdhury <quic_schowdhu@quicinc.com>20Description:21 This file is used to reset the configuration of22 a dcc driver to the default configuration. When '1'23 is written to the file, all the previous addresses24 stored in the driver gets removed and users need to25 reconfigure addresses again.26 27What: /sys/kernel/debug/dcc/.../[list-number]/config28Date: December 202229Contact: Souradeep Chowdhury <quic_schowdhu@quicinc.com>30Description:31 This stores the addresses of the registers which32 can be read in case of a hardware crash or manual33 software triggers. The input addresses type34 can be one of following dcc instructions: read,35 write, read-write, and loop type. The lists need to36 be configured sequentially and not in a overlapping37 manner; e.g. users can jump to list x only after38 list y is configured and enabled. The input format for39 each type is as follows:40 41 i) Read instruction42 43 ::44 45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config46 47 where:48 49 <addr>50 The address to be read.51 52 <n>53 The addresses word count, starting from address <1>.54 Each word is 32 bits (4 bytes). If omitted, defaulted55 to 1.56 57 <bus type>58 The bus type, which can be either 'apb' or 'ahb'.59 The default is 'ahb' if leaved out.60 61 ii) Write instruction62 63 ::64 65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config66 67 where:68 69 <addr>70 The address to be written.71 72 <n>73 The value to be written at <addr>.74 75 <bus type>76 The bus type, which can be either 'apb' or 'ahb'.77 78 iii) Read-write instruction79 80 ::81 82 echo RW <addr> <n> <mask> > /sys/kernel/debug/dcc/../[list-number]/config83 84 where:85 86 <addr>87 The address to be read and written.88 89 <n>90 The value to be written at <addr>.91 92 <mask>93 The value mask.94 95 iv) Loop instruction96 97 ::98 99 echo L <loop count> <address count> <address>... > /sys/kernel/debug/dcc/../[list-number]/config100 101 where:102 103 <loop count>104 Number of iterations105 106 <address count>107 total number of addresses to be written108 109 <address>110 Space-separated list of addresses.111 112What: /sys/kernel/debug/dcc/.../[list-number]/enable113Date: December 2022114Contact: Souradeep Chowdhury <quic_schowdhu@quicinc.com>115Description:116 This debugfs interface is used for enabling the117 the dcc hardware. A file named "enable" is in the118 directory list number where users can enable/disable119 the specific list by writing boolean (1 or 0) to the120 file.121 122 On enabling the dcc, all the addresses specified123 by the user for the corresponding list is written124 into dcc sram which is read by the dcc hardware125 on manual or crash induced triggers. Lists must126 be configured and enabled sequentially, e.g. list127 2 can only be enabled when list 1 have so.128