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1What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink2Date: November 20143KernelVersion: 3.194Contact: Mathieu Poirier <mathieu.poirier@linaro.org>5Description: (RW) Add/remove a sink from a trace path. There can be multiple6 source for a single sink.7 8 ex::9 10 echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink11 12What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr13Date: November 201414KernelVersion: 3.1915Contact: Mathieu Poirier <mathieu.poirier@linaro.org>16Description: (RW) Disables write access to the Trace RAM by stopping the17 formatter after a defined number of words have been stored18 following the trigger event. The number of 32-bit words written19 into the Trace RAM following the trigger event is equal to the20 value stored in this register+1 (from ARM ETB-TRM).21 22What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp23Date: March 201624KernelVersion: 4.725Contact: Mathieu Poirier <mathieu.poirier@linaro.org>26Description: (Read) Defines the depth, in words, of the trace RAM in powers of27 2. The value is read directly from HW register RDP, 0x004.28 29What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts30Date: March 201631KernelVersion: 4.732Contact: Mathieu Poirier <mathieu.poirier@linaro.org>33Description: (Read) Shows the value held by the ETB status register. The value34 is read directly from HW register STS, 0x00C.35 36What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp37Date: March 201638KernelVersion: 4.739Contact: Mathieu Poirier <mathieu.poirier@linaro.org>40Description: (Read) Shows the value held by the ETB RAM Read Pointer register41 that is used to read entries from the Trace RAM over the APB42 interface. The value is read directly from HW register RRP,43 0x014.44 45What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp46Date: March 201647KernelVersion: 4.748Contact: Mathieu Poirier <mathieu.poirier@linaro.org>49Description: (Read) Shows the value held by the ETB RAM Write Pointer register50 that is used to sets the write pointer to write entries from51 the CoreSight bus into the Trace RAM. The value is read directly52 from HW register RWP, 0x018.53 54What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg55Date: March 201656KernelVersion: 4.757Contact: Mathieu Poirier <mathieu.poirier@linaro.org>58Description: (Read) Similar to "trigger_cntr" above except that this value is59 read directly from HW register TRG, 0x01C.60 61What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl62Date: March 201663KernelVersion: 4.764Contact: Mathieu Poirier <mathieu.poirier@linaro.org>65Description: (Read) Shows the value held by the ETB Control register. The value66 is read directly from HW register CTL, 0x020.67 68What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr69Date: March 201670KernelVersion: 4.771Contact: Mathieu Poirier <mathieu.poirier@linaro.org>72Description: (Read) Shows the value held by the ETB Formatter and Flush Status73 register. The value is read directly from HW register FFSR,74 0x300.75 76What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr77Date: March 201678KernelVersion: 4.779Contact: Mathieu Poirier <mathieu.poirier@linaro.org>80Description: (Read) Shows the value held by the ETB Formatter and Flush Control81 register. The value is read directly from HW register FFCR,82 0x304.83