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1What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source2Date: November 20143KernelVersion: 3.194Contact: Mathieu Poirier <mathieu.poirier@linaro.org>5Description: (RW) Enable/disable tracing on this specific trace entiry.6 Enabling a source implies the source has been configured7 properly and a sink has been identidifed for it. The path8 of coresight components linking the source to the sink is9 configured and managed automatically by the coresight framework.10 11What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx12Date: November 201413KernelVersion: 3.1914Contact: Mathieu Poirier <mathieu.poirier@linaro.org>15Description: Select which address comparator or pair (of comparators) to16 work with.17 18What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype19Date: November 201420KernelVersion: 3.1921Contact: Mathieu Poirier <mathieu.poirier@linaro.org>22Description: (RW) Used in conjunction with @addr_idx. Specifies23 characteristics about the address comparator being configure,24 for example the access type, the kind of instruction to trace,25 processor context ID to trigger on, etc. Individual fields in26 the access type register may vary on the version of the trace27 entity.28 29What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range30Date: November 201431KernelVersion: 3.1932Contact: Mathieu Poirier <mathieu.poirier@linaro.org>33Description: (RW) Used in conjunction with @addr_idx. Specifies the range of34 addresses to trigger on. Inclusion or exclusion is specified35 in the corresponding access type register.36 37What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single38Date: November 201439KernelVersion: 3.1940Contact: Mathieu Poirier <mathieu.poirier@linaro.org>41Description: (RW) Used in conjunction with @addr_idx. Specifies the single42 address to trigger on, highly influenced by the configuration43 options of the corresponding access type register.44 45What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start46Date: November 201447KernelVersion: 3.1948Contact: Mathieu Poirier <mathieu.poirier@linaro.org>49Description: (RW) Used in conjunction with @addr_idx. Specifies the single50 address to start tracing on, highly influenced by the51 configuration options of the corresponding access type register.52 53What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop54Date: November 201455KernelVersion: 3.1956Contact: Mathieu Poirier <mathieu.poirier@linaro.org>57Description: (RW) Used in conjunction with @addr_idx. Specifies the single58 address to stop tracing on, highly influenced by the59 configuration options of the corresponding access type register.60 61What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx62Date: November 201463KernelVersion: 3.1964Contact: Mathieu Poirier <mathieu.poirier@linaro.org>65Description: (RW) Specifies the counter to work on.66 67What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event68Date: November 201469KernelVersion: 3.1970Contact: Mathieu Poirier <mathieu.poirier@linaro.org>71Description: (RW) Used in conjunction with cntr_idx, give access to the72 counter event register.73 74What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val75Date: November 201476KernelVersion: 3.1977Contact: Mathieu Poirier <mathieu.poirier@linaro.org>78Description: (RW) Used in conjunction with cntr_idx, give access to the79 counter value register.80 81What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_val82Date: November 201483KernelVersion: 3.1984Contact: Mathieu Poirier <mathieu.poirier@linaro.org>85Description: (RW) Used in conjunction with cntr_idx, give access to the86 counter reload value register.87 88What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_event89Date: November 201490KernelVersion: 3.1991Contact: Mathieu Poirier <mathieu.poirier@linaro.org>92Description: (RW) Used in conjunction with cntr_idx, give access to the93 counter reload event register.94 95What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_idx96Date: November 201497KernelVersion: 3.1998Contact: Mathieu Poirier <mathieu.poirier@linaro.org>99Description: (RW) Specifies the index of the context ID register to be100 selected.101 102What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_mask103Date: November 2014104KernelVersion: 3.19105Contact: Mathieu Poirier <mathieu.poirier@linaro.org>106Description: (RW) Mask to apply to all the context ID comparator.107 108What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_pid109Date: November 2014110KernelVersion: 3.19111Contact: Mathieu Poirier <mathieu.poirier@linaro.org>112Description: (RW) Used with the ctxid_idx, specify with context ID to trigger113 on.114 115What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_event116Date: November 2014117KernelVersion: 3.19118Contact: Mathieu Poirier <mathieu.poirier@linaro.org>119Description: (RW) Defines which event triggers a trace.120 121What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/etmsr122Date: November 2014123KernelVersion: 3.19124Contact: Mathieu Poirier <mathieu.poirier@linaro.org>125Description: (RW) Gives access to the ETM status register, which holds126 programming information and status on certains events.127 128What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/fifofull_level129Date: November 2014130KernelVersion: 3.19131Contact: Mathieu Poirier <mathieu.poirier@linaro.org>132Description: (RW) Number of byte left in the fifo before considering it full.133 Depending on the tracer's version, can also hold threshold for134 data suppression.135 136What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mode137Date: November 2014138KernelVersion: 3.19139Contact: Mathieu Poirier <mathieu.poirier@linaro.org>140Description: (RW) Interface with the driver's 'mode' field, controlling141 various aspect of the trace entity such as time stamping,142 context ID size and cycle accurate tracing. Driver specific143 and bound to change depending on the driver.144 145What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_addr_cmp146Date: November 2014147KernelVersion: 3.19148Contact: Mathieu Poirier <mathieu.poirier@linaro.org>149Description: (Read) Provides the number of address comparators pairs accessible150 on a trace unit, as specified by bit 3:0 of register ETMCCR.151 152What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_cntr153Date: November 2014154KernelVersion: 3.19155Contact: Mathieu Poirier <mathieu.poirier@linaro.org>156Description: (Read) Provides the number of counters accessible on a trace unit,157 as specified by bit 15:13 of register ETMCCR.158 159What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_ctxid_cmp160Date: November 2014161KernelVersion: 3.19162Contact: Mathieu Poirier <mathieu.poirier@linaro.org>163Description: (Read) Provides the number of context ID comparator available on a164 trace unit, as specified by bit 25:24 of register ETMCCR.165 166What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/reset167Date: November 2014168KernelVersion: 3.19169Contact: Mathieu Poirier <mathieu.poirier@linaro.org>170Description: (Write) Cancels all configuration on a trace unit and set it back171 to its boot configuration.172 173What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_12_event174Date: November 2014175KernelVersion: 3.19176Contact: Mathieu Poirier <mathieu.poirier@linaro.org>177Description: (RW) Defines the event that causes the sequencer to transition178 from state 1 to state 2.179 180What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_13_event181Date: November 2014182KernelVersion: 3.19183Contact: Mathieu Poirier <mathieu.poirier@linaro.org>184Description: (RW) Defines the event that causes the sequencer to transition185 from state 1 to state 3.186 187What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_21_event188Date: November 2014189KernelVersion: 3.19190Contact: Mathieu Poirier <mathieu.poirier@linaro.org>191Description: (RW) Defines the event that causes the sequencer to transition192 from state 2 to state 1.193 194What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_23_event195Date: November 2014196KernelVersion: 3.19197Contact: Mathieu Poirier <mathieu.poirier@linaro.org>198Description: (RW) Defines the event that causes the sequencer to transition199 from state 2 to state 3.200 201What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_31_event202Date: November 2014203KernelVersion: 3.19204Contact: Mathieu Poirier <mathieu.poirier@linaro.org>205Description: (RW) Defines the event that causes the sequencer to transition206 from state 3 to state 1.207 208What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_32_event209Date: November 2014210KernelVersion: 3.19211Contact: Mathieu Poirier <mathieu.poirier@linaro.org>212Description: (RW) Defines the event that causes the sequencer to transition213 from state 3 to state 2.214 215What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/curr_seq_state216Date: November 2014217KernelVersion: 3.19218Contact: Mathieu Poirier <mathieu.poirier@linaro.org>219Description: (Read) Holds the current state of the sequencer.220 221What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/sync_freq222Date: November 2014223KernelVersion: 3.19224Contact: Mathieu Poirier <mathieu.poirier@linaro.org>225Description: (RW) Holds the trace synchronization frequency value - must be226 programmed with the various implementation behavior in mind.227 228What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/timestamp_event229Date: November 2014230KernelVersion: 3.19231Contact: Mathieu Poirier <mathieu.poirier@linaro.org>232Description: (RW) Defines an event that requests the insertion of a timestamp233 into the trace stream.234 235What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/traceid236Date: November 2014237KernelVersion: 3.19238Contact: Mathieu Poirier <mathieu.poirier@linaro.org>239Description: (RO) Holds the trace ID that will appear in the trace stream240 coming from this trace entity.241 242What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event243Date: November 2014244KernelVersion: 3.19245Contact: Mathieu Poirier <mathieu.poirier@linaro.org>246Description: (RW) Define the event that controls the trigger.247 248What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cpu249Date: October 2015250KernelVersion: 4.4251Contact: Mathieu Poirier <mathieu.poirier@linaro.org>252Description: (RO) Holds the cpu number this tracer is affined to.253 254What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr255Date: September 2015256KernelVersion: 4.4257Contact: Mathieu Poirier <mathieu.poirier@linaro.org>258Description: (RO) Print the content of the ETM Configuration Code register259 (0x004). The value is read directly from the HW.260 261What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccer262Date: September 2015263KernelVersion: 4.4264Contact: Mathieu Poirier <mathieu.poirier@linaro.org>265Description: (RO) Print the content of the ETM Configuration Code Extension266 register (0x1e8). The value is read directly from the HW.267 268What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmscr269Date: September 2015270KernelVersion: 4.4271Contact: Mathieu Poirier <mathieu.poirier@linaro.org>272Description: (RO) Print the content of the ETM System Configuration273 register (0x014). The value is read directly from the HW.274 275What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmidr276Date: September 2015277KernelVersion: 4.4278Contact: Mathieu Poirier <mathieu.poirier@linaro.org>279Description: (RO) Print the content of the ETM ID register (0x1e4). The280 value is read directly from the HW.281 282What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmcr283Date: September 2015284KernelVersion: 4.4285Contact: Mathieu Poirier <mathieu.poirier@linaro.org>286Description: (RO) Print the content of the ETM Main Control register (0x000).287 The value is read directly from the HW.288 289What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtraceidr290Date: September 2015291KernelVersion: 4.4292Contact: Mathieu Poirier <mathieu.poirier@linaro.org>293Description: (RO) Print the content of the ETM Trace ID register (0x200).294 The value is read directly from the HW.295 296What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmteevr297Date: September 2015298KernelVersion: 4.4299Contact: Mathieu Poirier <mathieu.poirier@linaro.org>300Description: (RO) Print the content of the ETM Trace Enable Event register301 (0x020). The value is read directly from the HW.302 303What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtsscr304Date: September 2015305KernelVersion: 4.4306Contact: Mathieu Poirier <mathieu.poirier@linaro.org>307Description: (RO) Print the content of the ETM Trace Start/Stop Control308 register (0x018). The value is read directly from the HW.309 310What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr1311Date: September 2015312KernelVersion: 4.4313Contact: Mathieu Poirier <mathieu.poirier@linaro.org>314Description: (RO) Print the content of the ETM Enable Control #1315 register (0x024). The value is read directly from the HW.316 317What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr2318Date: September 2015319KernelVersion: 4.4320Contact: Mathieu Poirier <mathieu.poirier@linaro.org>321Description: (RO) Print the content of the ETM Enable Control #2322 register (0x01c). The value is read directly from the HW.323