527 lines · plain
1What: /sys/bus/coresight/devices/etm<N>/enable_source2Date: April 20153KernelVersion: 4.014Contact: Mathieu Poirier <mathieu.poirier@linaro.org>5Description: (RW) Enable/disable tracing on this specific trace entiry.6 Enabling a source implies the source has been configured7 properly and a sink has been identidifed for it. The path8 of coresight components linking the source to the sink is9 configured and managed automatically by the coresight framework.10 11What: /sys/bus/coresight/devices/etm<N>/cpu12Date: April 201513KernelVersion: 4.0114Contact: Mathieu Poirier <mathieu.poirier@linaro.org>15Description: (Read) The CPU this tracing entity is associated with.16 17What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp18Date: April 201519KernelVersion: 4.0120Contact: Mathieu Poirier <mathieu.poirier@linaro.org>21Description: (Read) Indicates the number of PE comparator inputs that are22 available for tracing.23 24What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp25Date: April 201526KernelVersion: 4.0127Contact: Mathieu Poirier <mathieu.poirier@linaro.org>28Description: (Read) Indicates the number of address comparator pairs that are29 available for tracing.30 31What: /sys/bus/coresight/devices/etm<N>/nr_cntr32Date: April 201533KernelVersion: 4.0134Contact: Mathieu Poirier <mathieu.poirier@linaro.org>35Description: (Read) Indicates the number of counters that are available for36 tracing.37 38What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp39Date: April 201540KernelVersion: 4.0141Contact: Mathieu Poirier <mathieu.poirier@linaro.org>42Description: (Read) Indicates how many external inputs are implemented.43 44What: /sys/bus/coresight/devices/etm<N>/numcidc45Date: April 201546KernelVersion: 4.0147Contact: Mathieu Poirier <mathieu.poirier@linaro.org>48Description: (Read) Indicates the number of Context ID comparators that are49 available for tracing.50 51What: /sys/bus/coresight/devices/etm<N>/numvmidc52Date: April 201553KernelVersion: 4.0154Contact: Mathieu Poirier <mathieu.poirier@linaro.org>55Description: (Read) Indicates the number of VMID comparators that are available56 for tracing.57 58What: /sys/bus/coresight/devices/etm<N>/nrseqstate59Date: April 201560KernelVersion: 4.0161Contact: Mathieu Poirier <mathieu.poirier@linaro.org>62Description: (Read) Indicates the number of sequencer states that are63 implemented.64 65What: /sys/bus/coresight/devices/etm<N>/nr_resource66Date: April 201567KernelVersion: 4.0168Contact: Mathieu Poirier <mathieu.poirier@linaro.org>69Description: (Read) Indicates the number of resource selection pairs that are70 available for tracing.71 72What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp73Date: April 201574KernelVersion: 4.0175Contact: Mathieu Poirier <mathieu.poirier@linaro.org>76Description: (Read) Indicates the number of single-shot comparator controls that77 are available for tracing.78 79What: /sys/bus/coresight/devices/etm<N>/reset80Date: April 201581KernelVersion: 4.0182Contact: Mathieu Poirier <mathieu.poirier@linaro.org>83Description: (Write) Cancels all configuration on a trace unit and set it back84 to its boot configuration.85 86What: /sys/bus/coresight/devices/etm<N>/mode87Date: April 201588KernelVersion: 4.0189Contact: Mathieu Poirier <mathieu.poirier@linaro.org>90Description: (RW) Controls various modes supported by this ETM, for example91 P0 instruction tracing, branch broadcast, cycle counting and92 context ID tracing.93 94What: /sys/bus/coresight/devices/etm<N>/pe95Date: April 201596KernelVersion: 4.0197Contact: Mathieu Poirier <mathieu.poirier@linaro.org>98Description: (RW) Controls which PE to trace.99 100What: /sys/bus/coresight/devices/etm<N>/event101Date: April 2015102KernelVersion: 4.01103Contact: Mathieu Poirier <mathieu.poirier@linaro.org>104Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3.105 106What: /sys/bus/coresight/devices/etm<N>/event_instren107Date: April 2015108KernelVersion: 4.01109Contact: Mathieu Poirier <mathieu.poirier@linaro.org>110Description: (RW) Controls the behavior of the events in bank 0 to 3.111 112What: /sys/bus/coresight/devices/etm<N>/event_ts113Date: April 2015114KernelVersion: 4.01115Contact: Mathieu Poirier <mathieu.poirier@linaro.org>116Description: (RW) Controls the insertion of global timestamps in the trace117 streams.118 119What: /sys/bus/coresight/devices/etm<N>/syncfreq120Date: April 2015121KernelVersion: 4.01122Contact: Mathieu Poirier <mathieu.poirier@linaro.org>123Description: (RW) Controls how often trace synchronization requests occur.124 125What: /sys/bus/coresight/devices/etm<N>/cyc_threshold126Date: April 2015127KernelVersion: 4.01128Contact: Mathieu Poirier <mathieu.poirier@linaro.org>129Description: (RW) Sets the threshold value for cycle counting.130 131What: /sys/bus/coresight/devices/etm<N>/bb_ctrl132Date: April 2015133KernelVersion: 4.01134Contact: Mathieu Poirier <mathieu.poirier@linaro.org>135Description: (RW) Controls which regions in the memory map are enabled to136 use branch broadcasting.137 138What: /sys/bus/coresight/devices/etm<N>/event_vinst139Date: April 2015140KernelVersion: 4.01141Contact: Mathieu Poirier <mathieu.poirier@linaro.org>142Description: (RW) Controls instruction trace filtering.143 144What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst145Date: April 2015146KernelVersion: 4.01147Contact: Mathieu Poirier <mathieu.poirier@linaro.org>148Description: (RW) In Secure state, each bit controls whether instruction149 tracing is enabled for the corresponding exception level.150 151What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst152Date: April 2015153KernelVersion: 4.01154Contact: Mathieu Poirier <mathieu.poirier@linaro.org>155Description: (RW) In non-secure state, each bit controls whether instruction156 tracing is enabled for the corresponding exception level.157 158What: /sys/bus/coresight/devices/etm<N>/addr_idx159Date: April 2015160KernelVersion: 4.01161Contact: Mathieu Poirier <mathieu.poirier@linaro.org>162Description: (RW) Select which address comparator or pair (of comparators) to163 work with.164 165What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype166Date: April 2015167KernelVersion: 4.01168Contact: Mathieu Poirier <mathieu.poirier@linaro.org>169Description: (RW) Controls what type of comparison the trace unit performs.170 171What: /sys/bus/coresight/devices/etm<N>/addr_single172Date: April 2015173KernelVersion: 4.01174Contact: Mathieu Poirier <mathieu.poirier@linaro.org>175Description: (RW) Used to setup single address comparator values.176 177What: /sys/bus/coresight/devices/etm<N>/addr_range178Date: April 2015179KernelVersion: 4.01180Contact: Mathieu Poirier <mathieu.poirier@linaro.org>181Description: (RW) Used to setup address range comparator values.182 183What: /sys/bus/coresight/devices/etm<N>/seq_idx184Date: April 2015185KernelVersion: 4.01186Contact: Mathieu Poirier <mathieu.poirier@linaro.org>187Description: (RW) Select which sequensor.188 189What: /sys/bus/coresight/devices/etm<N>/seq_state190Date: April 2015191KernelVersion: 4.01192Contact: Mathieu Poirier <mathieu.poirier@linaro.org>193Description: (RW) Use this to set, or read, the sequencer state.194 195What: /sys/bus/coresight/devices/etm<N>/seq_event196Date: April 2015197KernelVersion: 4.01198Contact: Mathieu Poirier <mathieu.poirier@linaro.org>199Description: (RW) Moves the sequencer state to a specific state.200 201What: /sys/bus/coresight/devices/etm<N>/seq_reset_event202Date: April 2015203KernelVersion: 4.01204Contact: Mathieu Poirier <mathieu.poirier@linaro.org>205Description: (RW) Moves the sequencer to state 0 when a programmed event206 occurs.207 208What: /sys/bus/coresight/devices/etm<N>/cntr_idx209Date: April 2015210KernelVersion: 4.01211Contact: Mathieu Poirier <mathieu.poirier@linaro.org>212Description: (RW) Select which counter unit to work with.213 214What: /sys/bus/coresight/devices/etm<N>/cntrldvr215Date: April 2015216KernelVersion: 4.01217Contact: Mathieu Poirier <mathieu.poirier@linaro.org>218Description: (RW) This sets or returns the reload count value of the219 specific counter.220 221What: /sys/bus/coresight/devices/etm<N>/cntr_val222Date: April 2015223KernelVersion: 4.01224Contact: Mathieu Poirier <mathieu.poirier@linaro.org>225Description: (RW) This sets or returns the current count value of the226 specific counter.227 228What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl229Date: April 2015230KernelVersion: 4.01231Contact: Mathieu Poirier <mathieu.poirier@linaro.org>232Description: (RW) Controls the operation of the selected counter.233 234What: /sys/bus/coresight/devices/etm<N>/res_idx235Date: April 2015236KernelVersion: 4.01237Contact: Mathieu Poirier <mathieu.poirier@linaro.org>238Description: (RW) Select which resource selection unit to work with.239 240What: /sys/bus/coresight/devices/etm<N>/res_ctrl241Date: April 2015242KernelVersion: 4.01243Contact: Mathieu Poirier <mathieu.poirier@linaro.org>244Description: (RW) Controls the selection of the resources in the trace unit.245 246What: /sys/bus/coresight/devices/etm<N>/ctxid_idx247Date: April 2015248KernelVersion: 4.01249Contact: Mathieu Poirier <mathieu.poirier@linaro.org>250Description: (RW) Select which context ID comparator to work with.251 252What: /sys/bus/coresight/devices/etm<N>/ctxid_pid253Date: April 2015254KernelVersion: 4.01255Contact: Mathieu Poirier <mathieu.poirier@linaro.org>256Description: (RW) Get/Set the context ID comparator value to trigger on.257 258What: /sys/bus/coresight/devices/etm<N>/ctxid_masks259Date: April 2015260KernelVersion: 4.01261Contact: Mathieu Poirier <mathieu.poirier@linaro.org>262Description: (RW) Mask for all 8 context ID comparator value263 registers (if implemented).264 265What: /sys/bus/coresight/devices/etm<N>/vmid_idx266Date: April 2015267KernelVersion: 4.01268Contact: Mathieu Poirier <mathieu.poirier@linaro.org>269Description: (RW) Select which virtual machine ID comparator to work with.270 271What: /sys/bus/coresight/devices/etm<N>/vmid_val272Date: April 2015273KernelVersion: 4.01274Contact: Mathieu Poirier <mathieu.poirier@linaro.org>275Description: (RW) Get/Set the virtual machine ID comparator value to276 trigger on.277 278What: /sys/bus/coresight/devices/etm<N>/vmid_masks279Date: April 2015280KernelVersion: 4.01281Contact: Mathieu Poirier <mathieu.poirier@linaro.org>282Description: (RW) Mask for all 8 virtual machine ID comparator value283 registers (if implemented).284 285What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns286Date: December 2019287KernelVersion: 5.5288Contact: Mathieu Poirier <mathieu.poirier@linaro.org>289Description: (RW) Set the Exception Level matching bits for secure and290 non-secure exception levels.291 292What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop293Date: December 2019294KernelVersion: 5.5295Contact: Mathieu Poirier <mathieu.poirier@linaro.org>296Description: (RW) Access the start stop control register for PE input297 comparators.298 299What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view300Date: December 2019301KernelVersion: 5.5302Contact: Mathieu Poirier <mathieu.poirier@linaro.org>303Description: (Read) Print the current settings for the selected address304 comparator.305 306What: /sys/bus/coresight/devices/etm<N>/sshot_idx307Date: December 2019308KernelVersion: 5.5309Contact: Mathieu Poirier <mathieu.poirier@linaro.org>310Description: (RW) Select the single shot control register to access.311 312What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl313Date: December 2019314KernelVersion: 5.5315Contact: Mathieu Poirier <mathieu.poirier@linaro.org>316Description: (RW) Access the selected single shot control register.317 318What: /sys/bus/coresight/devices/etm<N>/sshot_status319Date: December 2019320KernelVersion: 5.5321Contact: Mathieu Poirier <mathieu.poirier@linaro.org>322Description: (Read) Print the current value of the selected single shot323 status register.324 325What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl326Date: December 2019327KernelVersion: 5.5328Contact: Mathieu Poirier <mathieu.poirier@linaro.org>329Description: (RW) Access the selected single show PE comparator control330 register.331 332What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr333Date: April 2015334KernelVersion: 4.01335Contact: Mathieu Poirier <mathieu.poirier@linaro.org>336Description: (Read) Print the content of the OS Lock Status Register (0x304).337 The value it taken directly from the HW.338 339What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr340Date: April 2015341KernelVersion: 4.01342Contact: Mathieu Poirier <mathieu.poirier@linaro.org>343Description: (Read) Print the content of the Power Down Control Register344 (0x310). The value is taken directly from the HW.345 346What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr347Date: April 2015348KernelVersion: 4.01349Contact: Mathieu Poirier <mathieu.poirier@linaro.org>350Description: (Read) Print the content of the Power Down Status Register351 (0x314). The value is taken directly from the HW.352 353What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr354Date: April 2015355KernelVersion: 4.01356Contact: Mathieu Poirier <mathieu.poirier@linaro.org>357Description: (Read) Print the content of the SW Lock Status Register358 (0xFB4). The value is taken directly from the HW.359 360What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus361Date: April 2015362KernelVersion: 4.01363Contact: Mathieu Poirier <mathieu.poirier@linaro.org>364Description: (Read) Print the content of the Authentication Status Register365 (0xFB8). The value is taken directly from the HW.366 367What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid368Date: April 2015369KernelVersion: 4.01370Contact: Mathieu Poirier <mathieu.poirier@linaro.org>371Description: (Read) Print the content of the Device ID Register372 (0xFC8). The value is taken directly from the HW.373 374What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch375Date: January 2021376KernelVersion: 5.12377Contact: Mathieu Poirier <mathieu.poirier@linaro.org>378Description: (Read) Print the content of the Device Architecture Register379 (offset 0xFBC). The value is taken directly read380 from the HW.381 382What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype383Date: April 2015384KernelVersion: 4.01385Contact: Mathieu Poirier <mathieu.poirier@linaro.org>386Description: (Read) Print the content of the Device Type Register387 (0xFCC). The value is taken directly from the HW.388 389What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0390Date: April 2015391KernelVersion: 4.01392Contact: Mathieu Poirier <mathieu.poirier@linaro.org>393Description: (Read) Print the content of the Peripheral ID0 Register394 (0xFE0). The value is taken directly from the HW.395 396What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1397Date: April 2015398KernelVersion: 4.01399Contact: Mathieu Poirier <mathieu.poirier@linaro.org>400Description: (Read) Print the content of the Peripheral ID1 Register401 (0xFE4). The value is taken directly from the HW.402 403What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2404Date: April 2015405KernelVersion: 4.01406Contact: Mathieu Poirier <mathieu.poirier@linaro.org>407Description: (Read) Print the content of the Peripheral ID2 Register408 (0xFE8). The value is taken directly from the HW.409 410What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3411Date: April 2015412KernelVersion: 4.01413Contact: Mathieu Poirier <mathieu.poirier@linaro.org>414Description: (Read) Print the content of the Peripheral ID3 Register415 (0xFEC). The value is taken directly from the HW.416 417What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig418Date: February 2016419KernelVersion: 4.07420Contact: Mathieu Poirier <mathieu.poirier@linaro.org>421Description: (Read) Print the content of the trace configuration register422 (0x010) as currently set by SW.423 424What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid425Date: February 2016426KernelVersion: 4.07427Contact: Mathieu Poirier <mathieu.poirier@linaro.org>428Description: (Read) Print the content of the trace ID register (0x040).429 430What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0431Date: April 2015432KernelVersion: 4.01433Contact: Mathieu Poirier <mathieu.poirier@linaro.org>434Description: (Read) Returns the tracing capabilities of the trace unit (0x1E0).435 The value is taken directly from the HW.436 437What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1438Date: April 2015439KernelVersion: 4.01440Contact: Mathieu Poirier <mathieu.poirier@linaro.org>441Description: (Read) Returns the tracing capabilities of the trace unit (0x1E4).442 The value is taken directly from the HW.443 444What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2445Date: April 2015446KernelVersion: 4.01447Contact: Mathieu Poirier <mathieu.poirier@linaro.org>448Description: (Read) Returns the maximum size of the data value, data address,449 VMID, context ID and instruction address in the trace unit450 (0x1E8). The value is taken directly from the HW.451 452What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3453Date: April 2015454KernelVersion: 4.01455Contact: Mathieu Poirier <mathieu.poirier@linaro.org>456Description: (Read) Returns the value associated with various resources457 available to the trace unit. See the Trace Macrocell458 architecture specification for more details (0x1E8).459 The value is taken directly from the HW.460 461What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4462Date: April 2015463KernelVersion: 4.01464Contact: Mathieu Poirier <mathieu.poirier@linaro.org>465Description: (Read) Returns how many resources the trace unit supports (0x1F0).466 The value is taken directly from the HW.467 468What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5469Date: April 2015470KernelVersion: 4.01471Contact: Mathieu Poirier <mathieu.poirier@linaro.org>472Description: (Read) Returns how many resources the trace unit supports (0x1F4).473 The value is taken directly from the HW.474 475What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8476Date: April 2015477KernelVersion: 4.01478Contact: Mathieu Poirier <mathieu.poirier@linaro.org>479Description: (Read) Returns the maximum speculation depth of the instruction480 trace stream. (0x180). The value is taken directly from the HW.481 482What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9483Date: April 2015484KernelVersion: 4.01485Contact: Mathieu Poirier <mathieu.poirier@linaro.org>486Description: (Read) Returns the number of P0 right-hand keys that the trace unit487 can use (0x184). The value is taken directly from the HW.488 489What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10490Date: April 2015491KernelVersion: 4.01492Contact: Mathieu Poirier <mathieu.poirier@linaro.org>493Description: (Read) Returns the number of P1 right-hand keys that the trace unit494 can use (0x188). The value is taken directly from the HW.495 496What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11497Date: April 2015498KernelVersion: 4.01499Contact: Mathieu Poirier <mathieu.poirier@linaro.org>500Description: (Read) Returns the number of special P1 right-hand keys that the501 trace unit can use (0x18C). The value is taken directly from502 the HW.503 504What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12505Date: April 2015506KernelVersion: 4.01507Contact: Mathieu Poirier <mathieu.poirier@linaro.org>508Description: (Read) Returns the number of conditional P1 right-hand keys that509 the trace unit can use (0x190). The value is taken directly510 from the HW.511 512What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13513Date: April 2015514KernelVersion: 4.01515Contact: Mathieu Poirier <mathieu.poirier@linaro.org>516Description: (Read) Returns the number of special conditional P1 right-hand keys517 that the trace unit can use (0x194). The value is taken518 directly from the HW.519 520What: /sys/bus/coresight/devices/etm<N>/ts_source521Date: October 2022522KernelVersion: 6.1523Contact: Mathieu Poirier <mathieu.poirier@linaro.org> or Suzuki K Poulose <suzuki.poulose@arm.com>524Description: (Read) When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for525 trace session. Otherwise -1 indicates an unknown time source. Check526 trcidr0.tssize to see if a global timestamp is available.527