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1What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source2Date: April 20163KernelVersion: 4.74Contact: Mathieu Poirier <mathieu.poirier@linaro.org>5Description: (RW) Enable/disable tracing on this specific trace macrocell.6 Enabling the trace macrocell implies it has been configured7 properly and a sink has been identified for it. The path8 of coresight components linking the source to the sink is9 configured and managed automatically by the coresight framework.10 11What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable12Date: April 201613KernelVersion: 4.714Contact: Mathieu Poirier <mathieu.poirier@linaro.org>15Description: (RW) Provides access to the HW event enable register, used in16 conjunction with HW event bank select register.17 18What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select19Date: April 201620KernelVersion: 4.721Contact: Mathieu Poirier <mathieu.poirier@linaro.org>22Description: (RW) Gives access to the HW event block select register23 (STMHEBSR) in order to configure up to 256 channels. Used in24 conjunction with "hwevent_enable" register as described above.25 26What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable27Date: April 201628KernelVersion: 4.729Contact: Mathieu Poirier <mathieu.poirier@linaro.org>30Description: (RW) Provides access to the stimulus port enable register31 (STMSPER). Used in conjunction with "port_select" described32 below.33 34What: /sys/bus/coresight/devices/<memory_map>.stm/port_select35Date: April 201636KernelVersion: 4.737Contact: Mathieu Poirier <mathieu.poirier@linaro.org>38Description: (RW) Used to determine which bank of stimulus port bit in39 register STMSPER (see above) apply to.40 41What: /sys/bus/coresight/devices/<memory_map>.stm/status42Date: April 201643KernelVersion: 4.744Contact: Mathieu Poirier <mathieu.poirier@linaro.org>45Description: (Read) List various control and status registers. The specific46 layout and content is driver specific.47 48What: /sys/bus/coresight/devices/<memory_map>.stm/traceid49Date: April 201650KernelVersion: 4.751Contact: Mathieu Poirier <mathieu.poirier@linaro.org>52Description: (RW) Holds the trace ID that will appear in the trace stream53 coming from this trace entity.54