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1What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr2Date: November 20143KernelVersion: 3.194Contact: Mathieu Poirier <mathieu.poirier@linaro.org>5Description: (RW) Disables write access to the Trace RAM by stopping the6 formatter after a defined number of words have been stored7 following the trigger event. Additional interface for this8 driver are expected to be added as it matures.9 10What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz11Date: March 201612KernelVersion: 4.713Contact: Mathieu Poirier <mathieu.poirier@linaro.org>14Description: (Read) Defines the size, in 32-bit words, of the local RAM buffer.15 The value is read directly from HW register RSZ, 0x004.16 17What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts18Date: March 201619KernelVersion: 4.720Contact: Mathieu Poirier <mathieu.poirier@linaro.org>21Description: (Read) Shows the value held by the TMC status register. The value22 is read directly from HW register STS, 0x00C.23 24What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp25Date: March 201626KernelVersion: 4.727Contact: Mathieu Poirier <mathieu.poirier@linaro.org>28Description: (Read) Shows the value held by the TMC RAM Read Pointer register29 that is used to read entries from the Trace RAM over the APB30 interface. The value is read directly from HW register RRP,31 0x014.32 33What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp34Date: March 201635KernelVersion: 4.736Contact: Mathieu Poirier <mathieu.poirier@linaro.org>37Description: (Read) Shows the value held by the TMC RAM Write Pointer register38 that is used to sets the write pointer to write entries from39 the CoreSight bus into the Trace RAM. The value is read directly40 from HW register RWP, 0x018.41 42What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg43Date: March 201644KernelVersion: 4.745Contact: Mathieu Poirier <mathieu.poirier@linaro.org>46Description: (Read) Similar to "trigger_cntr" above except that this value is47 read directly from HW register TRG, 0x01C.48 49What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl50Date: March 201651KernelVersion: 4.752Contact: Mathieu Poirier <mathieu.poirier@linaro.org>53Description: (Read) Shows the value held by the TMC Control register. The value54 is read directly from HW register CTL, 0x020.55 56What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr57Date: March 201658KernelVersion: 4.759Contact: Mathieu Poirier <mathieu.poirier@linaro.org>60Description: (Read) Shows the value held by the TMC Formatter and Flush Status61 register. The value is read directly from HW register FFSR,62 0x300.63 64What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr65Date: March 201666KernelVersion: 4.767Contact: Mathieu Poirier <mathieu.poirier@linaro.org>68Description: (Read) Shows the value held by the TMC Formatter and Flush Control69 register. The value is read directly from HW register FFCR,70 0x304.71 72What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode73Date: March 201674KernelVersion: 4.775Contact: Mathieu Poirier <mathieu.poirier@linaro.org>76Description: (Read) Shows the value held by the TMC Mode register, which77 indicate the mode the device has been configured to enact. The78 The value is read directly from the MODE register, 0x028.79 80What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid81Date: March 201682KernelVersion: 4.783Contact: Mathieu Poirier <mathieu.poirier@linaro.org>84Description: (Read) Indicates the capabilities of the Coresight TMC.85 The value is read directly from the DEVID register, 0xFC8,86 87What: /sys/bus/coresight/devices/<memory_map>.tmc/buffer_size88Date: December 201889KernelVersion: 4.1990Contact: Mathieu Poirier <mathieu.poirier@linaro.org>91Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS92 mode. Writable only for TMC-ETR configurations. The value93 should be aligned to the kernel pagesize.94 95What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_modes_available96Date: August 202397KernelVersion: 6.798Contact: Anshuman Khandual <anshuman.khandual@arm.com>99Description: (Read) Shows all supported Coresight TMC-ETR buffer modes available100 for the users to configure explicitly. This file is available only101 for TMC ETR devices.102 103What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_mode_preferred104Date: August 2023105KernelVersion: 6.7106Contact: Anshuman Khandual <anshuman.khandual@arm.com>107Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could108 only provide a mode which is supported for a given ETR device. This109 file is available only for TMC ETR devices.110