260 lines · plain
1What: /sys/bus/coresight/devices/<tpdm-name>/integration_test2Date: January 20233KernelVersion 6.24Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>5Description:6 (Write) Run integration test for tpdm. Integration test7 will generate test data for tpdm. It can help to make8 sure that the trace path is enabled and the link configurations9 are fine.10 11 Accepts only one of the 2 values - 1 or 2.12 1 : Generate 64 bits data13 2 : Generate 32 bits data14 15What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset16Date: March 202317KernelVersion 6.718Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>19Description:20 (Write) Reset the dataset of the tpdm.21 22 Accepts only one value - 1.23 1 : Reset the dataset of the tpdm24 25What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type26Date: March 202327KernelVersion 6.728Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>29Description:30 (RW) Set/Get the trigger type of the DSB for tpdm.31 32 Accepts only one of the 2 values - 0 or 1.33 0 : Set the DSB trigger type to false34 1 : Set the DSB trigger type to true35 36What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts37Date: March 202338KernelVersion 6.739Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>40Description:41 (RW) Set/Get the trigger timestamp of the DSB for tpdm.42 43 Accepts only one of the 2 values - 0 or 1.44 0 : Set the DSB trigger type to false45 1 : Set the DSB trigger type to true46 47What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode48Date: March 202349KernelVersion 6.750Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>51Description:52 (RW) Set/Get the programming mode of the DSB for tpdm.53 54 Accepts the value needs to be greater than 0. What data55 bits do is listed below.56 Bit[0:1] : Test mode control bit for choosing the inputs.57 Bit[3] : Set to 0 for low performance mode. Set to 1 for high58 performance mode.59 Bit[4:8] : Select byte lane for high performance mode.60 61What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx62Date: March 202363KernelVersion 6.764Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>65Description:66 (RW) Set/Get the index number of the edge detection for the DSB67 subunit TPDM. Since there are at most 256 edge detections, this68 value ranges from 0 to 255.69 70What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val71Date: March 202372KernelVersion 6.773Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>74Description:75 Write a data to control the edge detection corresponding to76 the index number. Before writing data to this sysfs file,77 "ctrl_idx" should be written first to configure the index78 number of the edge detection which needs to be controlled.79 80 Accepts only one of the following values.81 0 - Rising edge detection82 1 - Falling edge detection83 2 - Rising and falling edge detection (toggle detection)84 85 86What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask87Date: March 202388KernelVersion 6.789Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>90Description:91 Write a data to mask the edge detection corresponding to the index92 number. Before writing data to this sysfs file, "ctrl_idx" should93 be written first to configure the index number of the edge detection94 which needs to be masked.95 96 Accepts only one of the 2 values - 0 or 1.97 98What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]99Date: March 2023100KernelVersion 6.7101Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>102Description:103 Read a set of the edge control value of the DSB in TPDM.104 105What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]106Date: March 2023107KernelVersion 6.7108Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>109Description:110 Read a set of the edge control mask of the DSB in TPDM.111 112What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]113Date: March 2023114KernelVersion 6.7115Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>116Description:117 (RW) Set/Get the value of the trigger pattern for the DSB118 subunit TPDM.119 120What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]121Date: March 2023122KernelVersion 6.7123Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>124Description:125 (RW) Set/Get the mask of the trigger pattern for the DSB126 subunit TPDM.127 128What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]129Date: March 2023130KernelVersion 6.7131Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>132Description:133 (RW) Set/Get the value of the pattern for the DSB subunit TPDM.134 135What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]136Date: March 2023137KernelVersion 6.7138Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>139Description:140 (RW) Set/Get the mask of the pattern for the DSB subunit TPDM.141 142What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts143Date: March 2023144KernelVersion 6.7145Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>146Description:147 (Write) Set the pattern timestamp of DSB tpdm. Read148 the pattern timestamp of DSB tpdm.149 150 Accepts only one of the 2 values - 0 or 1.151 0 : Disable DSB pattern timestamp.152 1 : Enable DSB pattern timestamp.153 154What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type155Date: March 2023156KernelVersion 6.7157Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>158Description:159 (Write) Set the pattern type of DSB tpdm. Read160 the pattern type of DSB tpdm.161 162 Accepts only one of the 2 values - 0 or 1.163 0 : Set the DSB pattern type to value.164 1 : Set the DSB pattern type to toggle.165 166What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]167Date: March 2023168KernelVersion 6.7169Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>170Description:171 (RW) Set/Get the MSR(mux select register) for the DSB subunit172 TPDM.173 174What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode175Date: January 2024176KernelVersion 6.9177Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>178Description: (Write) Set the data collection mode of CMB tpdm. Continuous179 change creates CMB data set elements on every CMBCLK edge.180 Trace-on-change creates CMB data set elements only when a new181 data set element differs in value from the previous element182 in a CMB data set.183 184 Accepts only one of the 2 values - 0 or 1.185 0 : Continuous CMB collection mode.186 1 : Trace-on-change CMB collection mode.187 188What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1]189Date: January 2024190KernelVersion 6.9191Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>192Description:193 (RW) Set/Get the value of the trigger pattern for the CMB194 subunit TPDM.195 196What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1]197Date: January 2024198KernelVersion 6.9199Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>200Description:201 (RW) Set/Get the mask of the trigger pattern for the CMB202 subunit TPDM.203 204What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1]205Date: January 2024206KernelVersion 6.9207Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>208Description:209 (RW) Set/Get the value of the pattern for the CMB subunit TPDM.210 211What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1]212Date: January 2024213KernelVersion 6.9214Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>215Description:216 (RW) Set/Get the mask of the pattern for the CMB subunit TPDM.217 218What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts219Date: January 2024220KernelVersion 6.9221Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>222Description:223 (Write) Set the pattern timestamp of CMB tpdm. Read224 the pattern timestamp of CMB tpdm.225 226 Accepts only one of the 2 values - 0 or 1.227 0 : Disable CMB pattern timestamp.228 1 : Enable CMB pattern timestamp.229 230What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts231Date: January 2024232KernelVersion 6.9233Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>234Description:235 (RW) Set/Get the trigger timestamp of the CMB for tpdm.236 237 Accepts only one of the 2 values - 0 or 1.238 0 : Set the CMB trigger type to false239 1 : Set the CMB trigger type to true240 241What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all242Date: January 2024243KernelVersion 6.9244Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>245Description:246 (RW) Read or write the status of timestamp upon all interface.247 Only value 0 and 1 can be written to this node. Set this node to 1 to request248 timestamp to all trace packet.249 Accepts only one of the 2 values - 0 or 1.250 0 : Disable the timestamp of all trace packets.251 1 : Enable the timestamp of all trace packets.252 253What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]254Date: January 2024255KernelVersion 6.9256Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>257Description:258 (RW) Set/Get the MSR(mux select register) for the CMB subunit259 TPDM.260