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1What: /sys/bus/cxl/flush2Date: Januarry, 20223KernelVersion: v5.184Contact: linux-cxl@vger.kernel.org5Description:6 (WO) If userspace manually unbinds a port the kernel schedules7 all descendant memdevs for unbind. Writing '1' to this attribute8 flushes that work.9 10 11What: /sys/bus/cxl/devices/memX/firmware_version12Date: December, 202013KernelVersion: v5.1214Contact: linux-cxl@vger.kernel.org15Description:16 (RO) "FW Revision" string as reported by the Identify17 Memory Device Output Payload in the CXL-2.018 specification.19 20 21What: /sys/bus/cxl/devices/memX/ram/size22Date: December, 202023KernelVersion: v5.1224Contact: linux-cxl@vger.kernel.org25Description:26 (RO) "Volatile Only Capacity" as bytes. Represents the27 identically named field in the Identify Memory Device Output28 Payload in the CXL-2.0 specification.29 30 31What: /sys/bus/cxl/devices/memX/ram/qos_class32Date: May, 202333KernelVersion: v6.834Contact: linux-cxl@vger.kernel.org35Description:36 (RO) For CXL host platforms that support "QoS Telemmetry"37 this attribute conveys a comma delimited list of platform38 specific cookies that identifies a QoS performance class39 for the volatile partition of the CXL mem device. These40 class-ids can be compared against a similar "qos_class"41 published for a root decoder. While it is not required42 that the endpoints map their local memory-class to a43 matching platform class, mismatches are not recommended44 and there are platform specific performance related45 side-effects that may result. First class-id is displayed.46 47 48What: /sys/bus/cxl/devices/memX/pmem/size49Date: December, 202050KernelVersion: v5.1251Contact: linux-cxl@vger.kernel.org52Description:53 (RO) "Persistent Only Capacity" as bytes. Represents the54 identically named field in the Identify Memory Device Output55 Payload in the CXL-2.0 specification.56 57 58What: /sys/bus/cxl/devices/memX/pmem/qos_class59Date: May, 202360KernelVersion: v6.861Contact: linux-cxl@vger.kernel.org62Description:63 (RO) For CXL host platforms that support "QoS Telemmetry"64 this attribute conveys a comma delimited list of platform65 specific cookies that identifies a QoS performance class66 for the persistent partition of the CXL mem device. These67 class-ids can be compared against a similar "qos_class"68 published for a root decoder. While it is not required69 that the endpoints map their local memory-class to a70 matching platform class, mismatches are not recommended71 and there are platform specific performance related72 side-effects that may result. First class-id is displayed.73 74 75What: /sys/bus/cxl/devices/memX/serial76Date: January, 202277KernelVersion: v5.1878Contact: linux-cxl@vger.kernel.org79Description:80 (RO) 64-bit serial number per the PCIe Device Serial Number81 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.282 Memory Device PCIe Capabilities and Extended Capabilities.83 84 85What: /sys/bus/cxl/devices/memX/numa_node86Date: January, 202287KernelVersion: v5.1888Contact: linux-cxl@vger.kernel.org89Description:90 (RO) If NUMA is enabled and the platform has affinitized the91 host PCI device for this memory device, emit the CPU node92 affinity for this device.93 94 95What: /sys/bus/cxl/devices/memX/security/state96Date: June, 202397KernelVersion: v6.598Contact: linux-cxl@vger.kernel.org99Description:100 (RO) Reading this file will display the CXL security state for101 that device. Such states can be: 'disabled', 'sanitize', when102 a sanitization is currently underway; or those available only103 for persistent memory: 'locked', 'unlocked' or 'frozen'. This104 sysfs entry is select/poll capable from userspace to notify105 upon completion of a sanitize operation.106 107 108What: /sys/bus/cxl/devices/memX/security/sanitize109Date: June, 2023110KernelVersion: v6.5111Contact: linux-cxl@vger.kernel.org112Description:113 (WO) Write a boolean 'true' string value to this attribute to114 sanitize the device to securely re-purpose or decommission it.115 This is done by ensuring that all user data and meta-data,116 whether it resides in persistent capacity, volatile capacity,117 or the LSA, is made permanently unavailable by whatever means118 is appropriate for the media type. This functionality requires119 the device to be disabled, that is, not actively decoding any120 HPA ranges. This permits avoiding explicit global CPU cache121 management, relying instead for it to be done when a region122 transitions between software programmed and hardware committed123 states. If this file is not present, then there is no hardware124 support for the operation.125 126 127What /sys/bus/cxl/devices/memX/security/erase128Date: June, 2023129KernelVersion: v6.5130Contact: linux-cxl@vger.kernel.org131Description:132 (WO) Write a boolean 'true' string value to this attribute to133 secure erase user data by changing the media encryption keys for134 all user data areas of the device. This functionality requires135 the device to be disabled, that is, not actively decoding any136 HPA ranges. This permits avoiding explicit global CPU cache137 management, relying instead for it to be done when a region138 transitions between software programmed and hardware committed139 states. If this file is not present, then there is no hardware140 support for the operation.141 142 143What: /sys/bus/cxl/devices/memX/firmware/144Date: April, 2023145KernelVersion: v6.5146Contact: linux-cxl@vger.kernel.org147Description:148 (RW) Firmware uploader mechanism. The different files under149 this directory can be used to upload and activate new150 firmware for CXL devices. The interfaces under this are151 documented in sysfs-class-firmware.152 153 154What: /sys/bus/cxl/devices/*/devtype155Date: June, 2021156KernelVersion: v5.14157Contact: linux-cxl@vger.kernel.org158Description:159 (RO) CXL device objects export the devtype attribute which160 mirrors the same value communicated in the DEVTYPE environment161 variable for uevents for devices on the "cxl" bus.162 163 164What: /sys/bus/cxl/devices/*/modalias165Date: December, 2021166KernelVersion: v5.18167Contact: linux-cxl@vger.kernel.org168Description:169 (RO) CXL device objects export the modalias attribute which170 mirrors the same value communicated in the MODALIAS environment171 variable for uevents for devices on the "cxl" bus.172 173 174What: /sys/bus/cxl/devices/portX/uport175Date: June, 2021176KernelVersion: v5.14177Contact: linux-cxl@vger.kernel.org178Description:179 (RO) CXL port objects are enumerated from either a platform180 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream181 port with CXL component registers. The 'uport' symlink connects182 the CXL portX object to the device that published the CXL port183 capability.184 185 186What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport187Date: January, 2023188KernelVersion: v6.3189Contact: linux-cxl@vger.kernel.org190Description:191 (RO) CXL port objects are instantiated for each upstream port in192 a CXL/PCIe switch, and for each endpoint to map the193 corresponding memory device into the CXL port hierarchy. When a194 descendant CXL port (switch or endpoint) is enumerated it is195 useful to know which 'dport' object in the parent CXL port196 routes to this descendant. The 'parent_dport' symlink points to197 the device representing the downstream port of a CXL switch that198 routes to {port,endpoint}X.199 200 201What: /sys/bus/cxl/devices/portX/dportY202Date: June, 2021203KernelVersion: v5.14204Contact: linux-cxl@vger.kernel.org205Description:206 (RO) CXL port objects are enumerated from either a platform207 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream208 port with CXL component registers. The 'dportY' symlink209 identifies one or more downstream ports that the upstream port210 may target in its decode of CXL memory resources. The 'Y'211 integer reflects the hardware port unique-id used in the212 hardware decoder target list.213 214 215What: /sys/bus/cxl/devices/portX/decoders_committed216Date: October, 2023217KernelVersion: v6.7218Contact: linux-cxl@vger.kernel.org219Description:220 (RO) A memory device is considered active when any of its221 decoders are in the "committed" state (See CXL 3.0 8.2.4.19.7222 CXL HDM Decoder n Control Register). Hotplug and destructive223 operations like "sanitize" are blocked while device is actively224 decoding a Host Physical Address range. Note that this number225 may be elevated without any regionX objects active or even226 enumerated, as this may be due to decoders established by227 platform firwmare or a previous kernel (kexec).228 229 230What: /sys/bus/cxl/devices/decoderX.Y231Date: June, 2021232KernelVersion: v5.14233Contact: linux-cxl@vger.kernel.org234Description:235 (RO) CXL decoder objects are enumerated from either a platform236 firmware description, or a CXL HDM decoder register set in a237 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder238 Capability Structure). The 'X' in decoderX.Y represents the239 cxl_port container of this decoder, and 'Y' represents the240 instance id of a given decoder resource.241 242 243What: /sys/bus/cxl/devices/decoderX.Y/{start,size}244Date: June, 2021245KernelVersion: v5.14246Contact: linux-cxl@vger.kernel.org247Description:248 (RO) The 'start' and 'size' attributes together convey the249 physical address base and number of bytes mapped in the250 decoder's decode window. For decoders of devtype251 "cxl_decoder_root" the address range is fixed. For decoders of252 devtype "cxl_decoder_switch" the address is bounded by the253 decode range of the cxl_port ancestor of the decoder's cxl_port,254 and dynamically updates based on the active memory regions in255 that address space.256 257 258What: /sys/bus/cxl/devices/decoderX.Y/locked259Date: June, 2021260KernelVersion: v5.14261Contact: linux-cxl@vger.kernel.org262Description:263 (RO) CXL HDM decoders have the capability to lock the264 configuration until the next device reset. For decoders of265 devtype "cxl_decoder_root" there is no standard facility to266 unlock them. For decoders of devtype "cxl_decoder_switch" a267 secondary bus reset, of the PCIe bridge that provides the bus268 for this decoders uport, unlocks / resets the decoder.269 270 271What: /sys/bus/cxl/devices/decoderX.Y/target_list272Date: June, 2021273KernelVersion: v5.14274Contact: linux-cxl@vger.kernel.org275Description:276 (RO) Display a comma separated list of the current decoder277 target configuration. The list is ordered by the current278 configured interleave order of the decoder's dport instances.279 Each entry in the list is a dport id.280 281 282What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}283Date: June, 2021284KernelVersion: v5.14285Contact: linux-cxl@vger.kernel.org286Description:287 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it288 represents a fixed memory window identified by platform289 firmware. A fixed window may only support a subset of memory290 types. The 'cap_*' attributes indicate whether persistent291 memory, volatile memory, accelerator memory, and / or expander292 memory may be mapped behind this decoder's memory window.293 294 295What: /sys/bus/cxl/devices/decoderX.Y/target_type296Date: June, 2021297KernelVersion: v5.14298Contact: linux-cxl@vger.kernel.org299Description:300 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it301 can optionally decode either accelerator memory (type-2) or302 expander memory (type-3). The 'target_type' attribute indicates303 the current setting which may dynamically change based on what304 memory regions are activated in this decode hierarchy.305 306 307What: /sys/bus/cxl/devices/endpointX/CDAT308Date: July, 2022309KernelVersion: v6.0310Contact: linux-cxl@vger.kernel.org311Description:312 (RO) If this sysfs entry is not present no DOE mailbox was313 found to support CDAT data. If it is present and the length of314 the data is 0 reading the CDAT data failed. Otherwise the CDAT315 data is reported.316 317 318What: /sys/bus/cxl/devices/decoderX.Y/mode319Date: May, 2022320KernelVersion: v6.0321Contact: linux-cxl@vger.kernel.org322Description:323 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it324 translates from a host physical address range, to a device local325 address range. Device-local address ranges are further split326 into a 'ram' (volatile memory) range and 'pmem' (persistent327 memory) range. The 'mode' attribute emits one of 'ram', 'pmem',328 'mixed', or 'none'. The 'mixed' indication is for error cases329 when a decoder straddles the volatile/persistent partition330 boundary, and 'none' indicates the decoder is not actively331 decoding, or no DPA allocation policy has been set.332 333 'mode' can be written, when the decoder is in the 'disabled'334 state, with either 'ram' or 'pmem' to set the boundaries for the335 next allocation.336 337 338What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource339Date: May, 2022340KernelVersion: v6.0341Contact: linux-cxl@vger.kernel.org342Description:343 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",344 and its 'dpa_size' attribute is non-zero, this attribute345 indicates the device physical address (DPA) base address of the346 allocation.347 348 349What: /sys/bus/cxl/devices/decoderX.Y/dpa_size350Date: May, 2022351KernelVersion: v6.0352Contact: linux-cxl@vger.kernel.org353Description:354 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it355 translates from a host physical address range, to a device local356 address range. The range, base address plus length in bytes, of357 DPA allocated to this decoder is conveyed in these 2 attributes.358 Allocations can be mutated as long as the decoder is in the359 disabled state. A write to 'dpa_size' releases the previous DPA360 allocation and then attempts to allocate from the free capacity361 in the device partition referred to by 'decoderX.Y/mode'.362 Allocate and free requests can only be performed on the highest363 instance number disabled decoder with non-zero size. I.e.364 allocations are enforced to occur in increasing 'decoderX.Y/id'365 order and frees are enforced to occur in decreasing366 'decoderX.Y/id' order.367 368 369What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways370Date: May, 2022371KernelVersion: v6.0372Contact: linux-cxl@vger.kernel.org373Description:374 (RO) The number of targets across which this decoder's host375 physical address (HPA) memory range is interleaved. The device376 maps every Nth block of HPA (of size ==377 'interleave_granularity') to consecutive DPA addresses. The378 decoder's position in the interleave is determined by the379 device's (endpoint or switch) switch ancestry. For root380 decoders their interleave is specified by platform firmware and381 they only specify a downstream target order for host bridges.382 383 384What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity385Date: May, 2022386KernelVersion: v6.0387Contact: linux-cxl@vger.kernel.org388Description:389 (RO) The number of consecutive bytes of host physical address390 space this decoder claims at address N before the decode rotates391 to the next target in the interleave at address N +392 interleave_granularity (assuming N is aligned to393 interleave_granularity).394 395 396What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region397Date: May, 2022, January, 2023398KernelVersion: v6.0 (pmem), v6.3 (ram)399Contact: linux-cxl@vger.kernel.org400Description:401 (RW) Write a string in the form 'regionZ' to start the process402 of defining a new persistent, or volatile memory region403 (interleave-set) within the decode range bounded by root decoder404 'decoderX.Y'. The value written must match the current value405 returned from reading this attribute. An atomic compare exchange406 operation is done on write to assign the requested id to a407 region and allocate the region-id for the next creation attempt.408 EBUSY is returned if the region name written does not match the409 current cached value.410 411 412What: /sys/bus/cxl/devices/decoderX.Y/delete_region413Date: May, 2022414KernelVersion: v6.0415Contact: linux-cxl@vger.kernel.org416Description:417 (WO) Write a string in the form 'regionZ' to delete that region,418 provided it is currently idle / not bound to a driver.419 420 421What: /sys/bus/cxl/devices/decoderX.Y/qos_class422Date: May, 2023423KernelVersion: v6.5424Contact: linux-cxl@vger.kernel.org425Description:426 (RO) For CXL host platforms that support "QoS Telemmetry" this427 root-decoder-only attribute conveys a platform specific cookie428 that identifies a QoS performance class for the CXL Window.429 This class-id can be compared against a similar "qos_class"430 published for each memory-type that an endpoint supports. While431 it is not required that endpoints map their local memory-class432 to a matching platform class, mismatches are not recommended and433 there are platform specific side-effects that may result.434 435 436What: /sys/bus/cxl/devices/regionZ/uuid437Date: May, 2022438KernelVersion: v6.0439Contact: linux-cxl@vger.kernel.org440Description:441 (RW) Write a unique identifier for the region. This field must442 be set for persistent regions and it must not conflict with the443 UUID of another region. For volatile ram regions this444 attribute is a read-only empty string.445 446 447What: /sys/bus/cxl/devices/regionZ/interleave_granularity448Date: May, 2022449KernelVersion: v6.0450Contact: linux-cxl@vger.kernel.org451Description:452 (RW) Set the number of consecutive bytes each device in the453 interleave set will claim. The possible interleave granularity454 values are determined by the CXL spec and the participating455 devices.456 457 458What: /sys/bus/cxl/devices/regionZ/interleave_ways459Date: May, 2022460KernelVersion: v6.0461Contact: linux-cxl@vger.kernel.org462Description:463 (RW) Configures the number of devices participating in the464 region is set by writing this value. Each device will provide465 1/interleave_ways of storage for the region.466 467 468What: /sys/bus/cxl/devices/regionZ/size469Date: May, 2022470KernelVersion: v6.0471Contact: linux-cxl@vger.kernel.org472Description:473 (RW) System physical address space to be consumed by the region.474 When written trigger the driver to allocate space out of the475 parent root decoder's address space. When read the size of the476 address space is reported and should match the span of the477 region's resource attribute. Size shall be set after the478 interleave configuration parameters. Once set it cannot be479 changed, only freed by writing 0. The kernel makes no guarantees480 that data is maintained over an address space freeing event, and481 there is no guarantee that a free followed by an allocate482 results in the same address being allocated.483 484 485What: /sys/bus/cxl/devices/regionZ/mode486Date: January, 2023487KernelVersion: v6.3488Contact: linux-cxl@vger.kernel.org489Description:490 (RO) The mode of a region is established at region creation time491 and dictates the mode of the endpoint decoder that comprise the492 region. For more details on the possible modes see493 /sys/bus/cxl/devices/decoderX.Y/mode494 495 496What: /sys/bus/cxl/devices/regionZ/resource497Date: May, 2022498KernelVersion: v6.0499Contact: linux-cxl@vger.kernel.org500Description:501 (RO) A region is a contiguous partition of a CXL root decoder502 address space. Region capacity is allocated by writing to the503 size attribute, the resulting physical address space determined504 by the driver is reflected here. It is therefore not useful to505 read this before writing a value to the size attribute.506 507 508What: /sys/bus/cxl/devices/regionZ/target[0..N]509Date: May, 2022510KernelVersion: v6.0511Contact: linux-cxl@vger.kernel.org512Description:513 (RW) Write an endpoint decoder object name to 'targetX' where X514 is the intended position of the endpoint device in the region515 interleave and N is the 'interleave_ways' setting for the516 region. ENXIO is returned if the write results in an impossible517 to map decode scenario, like the endpoint is unreachable at that518 position relative to the root decoder interleave. EBUSY is519 returned if the position in the region is already occupied, or520 if the region is not in a state to accept interleave521 configuration changes. EINVAL is returned if the object name is522 not an endpoint decoder. Once all positions have been523 successfully written a final validation for decode conflicts is524 performed before activating the region.525 526 527What: /sys/bus/cxl/devices/regionZ/commit528Date: May, 2022529KernelVersion: v6.0530Contact: linux-cxl@vger.kernel.org531Description:532 (RW) Write a boolean 'true' string value to this attribute to533 trigger the region to transition from the software programmed534 state to the actively decoding in hardware state. The commit535 operation in addition to validating that the region is in proper536 configured state, validates that the decoders are being537 committed in spec mandated order (last committed decoder id +538 1), and checks that the hardware accepts the commit request.539 Reading this value indicates whether the region is committed or540 not.541 542 543What: /sys/bus/cxl/devices/memX/trigger_poison_list544Date: April, 2023545KernelVersion: v6.4546Contact: linux-cxl@vger.kernel.org547Description:548 (WO) When a boolean 'true' is written to this attribute the549 memdev driver retrieves the poison list from the device. The550 list consists of addresses that are poisoned, or would result551 in poison if accessed, and the source of the poison. This552 attribute is only visible for devices supporting the553 capability. The retrieved errors are logged as kernel554 events when cxl_poison event tracing is enabled.555 556 557What: /sys/bus/cxl/devices/regionZ/accessY/read_bandwidth558 /sys/bus/cxl/devices/regionZ/accessY/write_banwidth559Date: Jan, 2024560KernelVersion: v6.9561Contact: linux-cxl@vger.kernel.org562Description:563 (RO) The aggregated read or write bandwidth of the region. The564 number is the accumulated read or write bandwidth of all CXL memory565 devices that contributes to the region in MB/s. It is566 identical data that should appear in567 /sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth or568 /sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth.569 See Documentation/ABI/stable/sysfs-devices-node. access0 provides570 the number to the closest initiator and access1 provides the571 number to the closest CPU.572 573 574What: /sys/bus/cxl/devices/regionZ/accessY/read_latency575 /sys/bus/cxl/devices/regionZ/accessY/write_latency576Date: Jan, 2024577KernelVersion: v6.9578Contact: linux-cxl@vger.kernel.org579Description:580 (RO) The read or write latency of the region. The number is581 the worst read or write latency of all CXL memory devices that582 contributes to the region in nanoseconds. It is identical data583 that should appear in584 /sys/devices/system/node/nodeX/accessY/initiators/read_latency or585 /sys/devices/system/node/nodeX/accessY/initiators/write_latency.586 See Documentation/ABI/stable/sysfs-devices-node. access0 provides587 the number to the closest initiator and access1 provides the588 number to the closest CPU.589