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1What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune2Date: October 20223KernelVersion: 6.14Contact: Yicong Yang <yangyicong@hisilicon.com>5Description: This directory contains files for tuning the PCIe link6 parameters(events). Each file is named after the event7 of the PCIe link.8 9 See Documentation/trace/hisi-ptt.rst for more information.10 11What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_cpl12Date: October 202213KernelVersion: 6.114Contact: Yicong Yang <yangyicong@hisilicon.com>15Description: (RW) Controls the weight of Tx completion TLPs, which influence16 the proportion of outbound completion TLPs on the PCIe link.17 The available tune data is [0, 1, 2]. Writing a negative value18 will return an error, and out of range values will be converted19 to 2. The value indicates a probable level of the event.20 21What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_np22Date: October 202223KernelVersion: 6.124Contact: Yicong Yang <yangyicong@hisilicon.com>25Description: (RW) Controls the weight of Tx non-posted TLPs, which influence26 the proportion of outbound non-posted TLPs on the PCIe link.27 The available tune data is [0, 1, 2]. Writing a negative value28 will return an error, and out of range values will be converted29 to 2. The value indicates a probable level of the event.30 31What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_p32Date: October 202233KernelVersion: 6.134Contact: Yicong Yang <yangyicong@hisilicon.com>35Description: (RW) Controls the weight of Tx posted TLPs, which influence the36 proportion of outbound posted TLPs on the PCIe link.37 The available tune data is [0, 1, 2]. Writing a negative value38 will return an error, and out of range values will be converted39 to 2. The value indicates a probable level of the event.40 41What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/rx_alloc_buf_level42Date: October 202243KernelVersion: 6.144Contact: Yicong Yang <yangyicong@hisilicon.com>45Description: (RW) Control the allocated buffer watermark for inbound packets.46 The packets will be stored in the buffer first and then transmitted47 either when the watermark reached or when timed out.48 The available tune data is [0, 1, 2]. Writing a negative value49 will return an error, and out of range values will be converted50 to 2. The value indicates a probable level of the event.51 52What: /sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/tx_alloc_buf_level53Date: October 202254KernelVersion: 6.155Contact: Yicong Yang <yangyicong@hisilicon.com>56Description: (RW) Control the allocated buffer watermark of outbound packets.57 The packets will be stored in the buffer first and then transmitted58 either when the watermark reached or when timed out.59 The available tune data is [0, 1, 2]. Writing a negative value60 will return an error, and out of range values will be converted61 to 2. The value indicates a probable level of the event.62 63What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters64Date: May 202365KernelVersion: 6.566Contact: Yicong Yang <yangyicong@hisilicon.com>67Description: This directory contains the files providing the PCIe Root Port filters68 information used for PTT trace. Each file is named after the supported69 Root Port device name <domain>:<bus>:<device>.<function>.70 71 See the description of the "filter" in Documentation/trace/hisi-ptt.rst72 for more information.73 74What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/multiselect75Date: May 202376KernelVersion: 6.577Contact: Yicong Yang <yangyicong@hisilicon.com>78Description: (Read) Indicates if this kind of filter can be selected at the same79 time as others filters, or must be used on it's own. 1 indicates80 the former case and 0 indicates the latter.81 82What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/<bdf>83Date: May 202384KernelVersion: 6.585Contact: Yicong Yang <yangyicong@hisilicon.com>86Description: (Read) Indicates the filter value of this Root Port filter, which87 can be used to control the TLP headers to trace by the PTT trace.88 89What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters90Date: May 202391KernelVersion: 6.592Contact: Yicong Yang <yangyicong@hisilicon.com>93Description: This directory contains the files providing the PCIe Requester filters94 information used for PTT trace. Each file is named after the supported95 Endpoint device name <domain>:<bus>:<device>.<function>.96 97 See the description of the "filter" in Documentation/trace/hisi-ptt.rst98 for more information.99 100What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/multiselect101Date: May 2023102KernelVersion: 6.5103Contact: Yicong Yang <yangyicong@hisilicon.com>104Description: (Read) Indicates if this kind of filter can be selected at the same105 time as others filters, or must be used on it's own. 1 indicates106 the former case and 0 indicates the latter.107 108What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/<bdf>109Date: May 2023110KernelVersion: 6.5111Contact: Yicong Yang <yangyicong@hisilicon.com>112Description: (Read) Indicates the filter value of this Requester filter, which113 can be used to control the TLP headers to trace by the PTT trace.114