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1What: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present2What: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present3What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present4What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present5What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present6What: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present7KernelVersion: 3.4.08Contact: linux-iio@vger.kernel.org9Description:10 Reading returns either '1' or '0'.11 12 '1' means that the clock in question is present.13 14 '0' means that the clock is missing.15 16What: /sys/bus/iio/devices/iio:deviceX/pllY_locked17KernelVersion: 3.4.018Contact: linux-iio@vger.kernel.org19Description:20 Reading returns either '1' or '0'. '1' means that the21 pllY is locked.22 23What: /sys/bus/iio/devices/iio:deviceX/sync_dividers24KernelVersion: 3.4.025Contact: linux-iio@vger.kernel.org26Description:27 Writing '1' triggers the clock distribution synchronization28 functionality. All dividers are reset and the channels start29 with their predefined phase offsets (out_altvoltageY_phase).30 Writing this file has the effect as driving the external31 /SYNC pin low.32