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1What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status2Date: February 20233KernelVersion: 6.44Contact: Nava kishore Manne <nava.kishore.manne@amd.com>5Description: (RO) Read fpga status.6 Read returns a hexadecimal value that tells the current status7 of the FPGA device. Each bit position in the status value is8 described Below(see ug570 chapter 9).9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration10 11 ====================== ==============================================12 BIT(0) 0: No CRC error13 1: CRC error14 15 BIT(1) 0: Decryptor security not set16 1: Decryptor security set17 18 BIT(2) 0: MMCMs/PLLs are not locked19 1: MMCMs/PLLs are locked20 21 BIT(3) 0: DCI not matched22 1: DCI matched23 24 BIT(4) 0: Start-up sequence has not finished25 1: Start-up sequence has finished26 27 BIT(5) 0: All I/Os are placed in High-Z state28 1: All I/Os behave as configured29 30 BIT(6) 0: Flip-flops and block RAM are write disabled31 1: Flip-flops and block RAM are write enabled32 33 BIT(7) 0: GHIGH_B_STATUS asserted34 1: GHIGH_B_STATUS deasserted35 36 BIT(8) to BIT(10) Status of the mode pins37 38 BIT(11) 0: Initialization has not finished39 1: Initialization finished40 41 BIT(12) Value on INIT_B_PIN pin42 43 BIT(13) 0: Signal not released44 1: Signal released45 46 BIT(14) Value on DONE_PIN pin.47 48 BIT(15) 0: No IDCODE_ERROR49 1: IDCODE_ERROR50 51 BIT(16) 0: No SECURITY_ERROR52 1: SECURITY_ERROR53 54 BIT(17) System Monitor over-temperature if set55 56 BIT(18) to BIT(20) Start-up state machine (0 to 7)57 Phase 0 = 00058 Phase 1 = 00159 Phase 2 = 01160 Phase 3 = 01061 Phase 4 = 11062 Phase 5 = 11163 Phase 6 = 10164 Phase 7 = 10065 66 BIT(25) to BIT(26) Indicates the detected bus width67 00 = x168 01 = x869 10 = x1670 11 = x3271 ====================== ==============================================72 73 The other bits are reserved.74