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1==========2Interrupts3==========4 52.5.2-rmk5:6 This is the first kernel that contains a major shake up of some of the7 major architecture-specific subsystems.8 9Firstly, it contains some pretty major changes to the way we handle the10MMU TLB. Each MMU TLB variant is now handled completely separately -11we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),12and finally TLB v4 (with write buffer, with I TLB invalidate entry).13There is more assembly code inside each of these functions, mainly to14allow more flexible TLB handling for the future.15 16Secondly, the IRQ subsystem.17 18The 2.5 kernels will be having major changes to the way IRQs are handled.19Unfortunately, this means that machine types that touch the irq_desc[]20array (basically all machine types) will break, and this means every21machine type that we currently have.22 23Lets take an example. On the Assabet with Neponset, we have::24 25 GPIO25 IRR:226 SA1100 ------------> Neponset -----------> SA111127 IIR:128 -----------> USAR29 IIR:030 -----------> SMC919631 32The way stuff currently works, all SA1111 interrupts are mutually33exclusive of each other - if you're processing one interrupt from the34SA1111 and another comes in, you have to wait for that interrupt to35finish processing before you can service the new interrupt. Eg, an36IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and37SMC9196 interrupts until it has finished transferring its multi-sector38data, which can be a long time. Note also that since we loop in the39SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.40 41 42The new approach brings several new ideas...43 44We introduce the concept of a "parent" and a "child". For example,45to the Neponset handler, the "parent" is GPIO25, and the "children"d46are SA1111, SMC9196 and USAR.47 48We also bring the idea of an IRQ "chip" (mainly to reduce the size of49the irqdesc array). This doesn't have to be a real "IC"; indeed the50SA11x0 IRQs are handled by two separate "chip" structures, one for51GPIO0-10, and another for all the rest. It is just a container for52the various operations (maybe this'll change to a better name).53This structure has the following operations::54 55 struct irqchip {56 /*57 * Acknowledge the IRQ.58 * If this is a level-based IRQ, then it is expected to mask the IRQ59 * as well.60 */61 void (*ack)(unsigned int irq);62 /*63 * Mask the IRQ in hardware.64 */65 void (*mask)(unsigned int irq);66 /*67 * Unmask the IRQ in hardware.68 */69 void (*unmask)(unsigned int irq);70 /*71 * Re-run the IRQ72 */73 void (*rerun)(unsigned int irq);74 /*75 * Set the type of the IRQ.76 */77 int (*type)(unsigned int irq, unsigned int, type);78 };79 80ack81 - required. May be the same function as mask for IRQs82 handled by do_level_IRQ.83mask84 - required.85unmask86 - required.87rerun88 - optional. Not required if you're using do_level_IRQ for all89 IRQs that use this 'irqchip'. Generally expected to re-trigger90 the hardware IRQ if possible. If not, may call the handler91 directly.92type93 - optional. If you don't support changing the type of an IRQ,94 it should be null so people can detect if they are unable to95 set the IRQ type.96 97For each IRQ, we keep the following information:98 99 - "disable" depth (number of disable_irq()s without enable_irq()s)100 - flags indicating what we can do with this IRQ (valid, probe,101 noautounmask) as before102 - status of the IRQ (probing, enable, etc)103 - chip104 - per-IRQ handler105 - irqaction structure list106 107The handler can be one of the 3 standard handlers - "level", "edge" and108"simple", or your own specific handler if you need to do something special.109 110The "level" handler is what we currently have - its pretty simple.111"edge" knows about the brokenness of such IRQ implementations - that you112need to leave the hardware IRQ enabled while processing it, and queueing113further IRQ events should the IRQ happen again while processing. The114"simple" handler is very basic, and does not perform any hardware115manipulation, nor state tracking. This is useful for things like the116SMC9196 and USAR above.117 118So, what's changed?119===================120 1211. Machine implementations must not write to the irqdesc array.122 1232. New functions to manipulate the irqdesc array. The first 4 are expected124 to be useful only to machine specific code. The last is recommended to125 only be used by machine specific code, but may be used in drivers if126 absolutely necessary.127 128 set_irq_chip(irq,chip)129 Set the mask/unmask methods for handling this IRQ130 131 set_irq_handler(irq,handler)132 Set the handler for this IRQ (level, edge, simple)133 134 set_irq_chained_handler(irq,handler)135 Set a "chained" handler for this IRQ - automatically136 enables this IRQ (eg, Neponset and SA1111 handlers).137 138 set_irq_flags(irq,flags)139 Set the valid/probe/noautoenable flags.140 141 set_irq_type(irq,type)142 Set active the IRQ edge(s)/level. This replaces the143 SA1111 INTPOL manipulation, and the set_GPIO_IRQ_edge()144 function. Type should be one of IRQ_TYPE_xxx defined in145 <linux/irq.h>146 1473. set_GPIO_IRQ_edge() is obsolete, and should be replaced by set_irq_type.148 1494. Direct access to SA1111 INTPOL is deprecated. Use set_irq_type instead.150 1515. A handler is expected to perform any necessary acknowledgement of the152 parent IRQ via the correct chip specific function. For instance, if153 the SA1111 is directly connected to a SA1110 GPIO, then you should154 acknowledge the SA1110 IRQ each time you re-read the SA1111 IRQ status.155 1566. For any child which doesn't have its own IRQ enable/disable controls157 (eg, SMC9196), the handler must mask or acknowledge the parent IRQ158 while the child handler is called, and the child handler should be the159 "simple" handler (not "edge" nor "level"). After the handler completes,160 the parent IRQ should be unmasked, and the status of all children must161 be re-checked for pending events. (see the Neponset IRQ handler for162 details).163 1647. fixup_irq() is gone, as is `arch/arm/mach-*/include/mach/irq.h`165 166Please note that this will not solve all problems - some of them are167hardware based. Mixing level-based and edge-based IRQs on the same168parent signal (eg neponset) is one such area where a software based169solution can't provide the full answer to low IRQ latency.170