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1.. SPDX-License-Identifier: GPL-2.02 3=========================4Introduction to LoongArch5=========================6 7LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are8currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit9version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels10(PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV011while applications run at PLV3. This document introduces the registers, basic12instruction set, virtual memory and some other topics of LoongArch.13 14Registers15=========16 17LoongArch registers include general purpose registers (GPRs), floating point18registers (FPRs), vector registers (VRs) and control status registers (CSRs)19used in privileged mode (PLV0).20 21GPRs22----23 24LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA3225and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers26are not architecturally special. (Except ``$r1``, which is hard-wired as the27link register of the BL instruction.)28 29The kernel uses a variant of the LoongArch register convention, as described in30the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:31 32================= =============== =================== ============33Name Alias Usage Preserved34 across calls35================= =============== =================== ============36``$r0`` ``$zero`` Constant zero Unused37``$r1`` ``$ra`` Return address No38``$r2`` ``$tp`` TLS/Thread pointer Unused39``$r3`` ``$sp`` Stack pointer Yes40``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No41``$r4``-``$r5`` ``$v0``-``$v1`` Return value No42``$r12``-``$r20`` ``$t0``-``$t8`` Temp registers No43``$r21`` ``$u0`` Percpu base address Unused44``$r22`` ``$fp`` Frame pointer Yes45``$r23``-``$r31`` ``$s0``-``$s8`` Static registers Yes46================= =============== =================== ============47 48.. Note::49 The register ``$r21`` is reserved in the ELF psABI, but used by the Linux50 kernel for storing the percpu base address. It normally has no ABI name,51 but is called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1``52 in some old code,however they are deprecated aliases of ``$a0`` and ``$a1``53 respectively.54 55FPRs56----57 58LoongArch has 32 FPRs ( ``$f0`` ~ ``$f31`` ) when FPU is present. Each one is5964-bit wide on the LA64 cores.60 61The floating-point register convention is the same as described in the62LoongArch ELF psABI spec:63 64================= ================== =================== ============65Name Alias Usage Preserved66 across calls67================= ================== =================== ============68``$f0``-``$f7`` ``$fa0``-``$fa7`` Argument registers No69``$f0``-``$f1`` ``$fv0``-``$fv1`` Return value No70``$f8``-``$f23`` ``$ft0``-``$ft15`` Temp registers No71``$f24``-``$f31`` ``$fs0``-``$fs7`` Static registers Yes72================= ================== =================== ============73 74.. Note::75 You may see ``$fv0`` or ``$fv1`` in some old code, however they are76 deprecated aliases of ``$fa0`` and ``$fa1`` respectively.77 78VRs79----80 81There are currently 2 vector extensions to LoongArch:82 83- LSX (Loongson SIMD eXtension) with 128-bit vectors,84- LASX (Loongson Advanced SIMD eXtension) with 256-bit vectors.85 86LSX brings ``$v0`` ~ ``$v31`` while LASX brings ``$x0`` ~ ``$x31`` as the vector87registers.88 89The VRs overlap with FPRs: for example, on a core implementing LSX and LASX,90the lower 128 bits of ``$x0`` is shared with ``$v0``, and the lower 64 bits of91``$v0`` is shared with ``$f0``; same with all other VRs.92 93CSRs94----95 96CSRs can only be accessed from privileged mode (PLV0):97 98================= ===================================== ==============99Address Full Name Abbrev Name100================= ===================================== ==============1010x0 Current Mode Information CRMD1020x1 Pre-exception Mode Information PRMD1030x2 Extension Unit Enable EUEN1040x3 Miscellaneous Control MISC1050x4 Exception Configuration ECFG1060x5 Exception Status ESTAT1070x6 Exception Return Address ERA1080x7 Bad (Faulting) Virtual Address BADV1090x8 Bad (Faulting) Instruction Word BADI1100xC Exception Entrypoint Address EENTRY1110x10 TLB Index TLBIDX1120x11 TLB Entry High-order Bits TLBEHI1130x12 TLB Entry Low-order Bits 0 TLBELO01140x13 TLB Entry Low-order Bits 1 TLBELO11150x18 Address Space Identifier ASID1160x19 Page Global Directory Address for PGDL117 Lower-half Address Space1180x1A Page Global Directory Address for PGDH119 Higher-half Address Space1200x1B Page Global Directory Address PGD1210x1C Page Walk Control for Lower- PWCL122 half Address Space1230x1D Page Walk Control for Higher- PWCH124 half Address Space1250x1E STLB Page Size STLBPS1260x1F Reduced Virtual Address Configuration RVACFG1270x20 CPU Identifier CPUID1280x21 Privileged Resource Configuration 1 PRCFG11290x22 Privileged Resource Configuration 2 PRCFG21300x23 Privileged Resource Configuration 3 PRCFG31310x30+n (0≤n≤15) Saved Data register SAVEn1320x40 Timer Identifier TID1330x41 Timer Configuration TCFG1340x42 Timer Value TVAL1350x43 Compensation of Timer Count CNTC1360x44 Timer Interrupt Clearing TICLR1370x60 LLBit Control LLBCTL1380x80 Implementation-specific Control 1 IMPCTL11390x81 Implementation-specific Control 2 IMPCTL21400x88 TLB Refill Exception Entrypoint TLBRENTRY141 Address1420x89 TLB Refill Exception BAD (Faulting) TLBRBADV143 Virtual Address1440x8A TLB Refill Exception Return Address TLBRERA1450x8B TLB Refill Exception Saved Data TLBRSAVE146 Register1470x8C TLB Refill Exception Entry Low-order TLBRELO0148 Bits 01490x8D TLB Refill Exception Entry Low-order TLBRELO1150 Bits 11510x8E TLB Refill Exception Entry High-order TLBEHI152 Bits1530x8F TLB Refill Exception Pre-exception TLBRPRMD154 Mode Information1550x90 Machine Error Control MERRCTL1560x91 Machine Error Information 1 MERRINFO11570x92 Machine Error Information 2 MERRINFO21580x93 Machine Error Exception Entrypoint MERRENTRY159 Address1600x94 Machine Error Exception Return MERRERA161 Address1620x95 Machine Error Exception Saved Data MERRSAVE163 Register1640x98 Cache TAGs CTAG1650x180+n (0≤n≤3) Direct Mapping Configuration Window n DMWn1660x200+2n (0≤n≤31) Performance Monitor Configuration n PMCFGn1670x201+2n (0≤n≤31) Performance Monitor Overall Counter n PMCNTn1680x300 Memory Load/Store WatchPoint MWPC169 Overall Control1700x301 Memory Load/Store WatchPoint MWPS171 Overall Status1720x310+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG1173 Configuration 11740x311+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG2175 Configuration 21760x312+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG3177 Configuration 31780x313+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG4179 Configuration 41800x380 Instruction Fetch WatchPoint FWPC181 Overall Control1820x381 Instruction Fetch WatchPoint FWPS183 Overall Status1840x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1185 Configuration 11860x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2187 Configuration 21880x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3189 Configuration 31900x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4191 Configuration 41920x500 Debug Register DBG1930x501 Debug Exception Return Address DERA1940x502 Debug Exception Saved Data Register DSAVE195================= ===================================== ==============196 197ERA, TLBRERA, MERRERA and DERA are sometimes also known as EPC, TLBREPC, MERREPC198and DEPC respectively.199 200Basic Instruction Set201=====================202 203Instruction formats204-------------------205 206LoongArch instructions are 32 bits wide, belonging to 9 basic instruction207formats (and variants of them):208 209=========== ==========================210Format name Composition211=========== ==========================2122R Opcode + Rj + Rd2133R Opcode + Rk + Rj + Rd2144R Opcode + Ra + Rk + Rj + Rd2152RI8 Opcode + I8 + Rj + Rd2162RI12 Opcode + I12 + Rj + Rd2172RI14 Opcode + I14 + Rj + Rd2182RI16 Opcode + I16 + Rj + Rd2191RI21 Opcode + I21L + Rj + I21H220I26 Opcode + I26L + I26H221=========== ==========================222 223Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for224"additional") are the source register operands. I8/I12/I14/I16/I21/I26 are225immediate operands of respective width. The longer I21 and I26 are stored226in separate higher and lower parts in the instruction word, denoted by the "L"227and "H" suffixes.228 229List of Instructions230--------------------231 232For brevity, only instruction names (mnemonics) are listed here; please see the233:ref:`References <loongarch-references>` for details.234 235 2361. Arithmetic Instructions::237 238 ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D239 SLT SLTU SLTI SLTUI240 AND OR NOR XOR ANDN ORN ANDI ORI XORI241 MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU242 MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU243 PCADDI PCADDU12I PCADDU18I244 LU12I.W LU32I.D LU52I.D ADDU16I.D245 2462. Bit-shift Instructions::247 248 SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W249 SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D250 2513. Bit-manipulation Instructions::252 253 EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D254 BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D255 REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D256 MASKEQZ MASKNEZ257 2584. Branch Instructions::259 260 BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL261 2625. Load/Store Instructions::263 264 LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D265 LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D266 LDPTR.W LDPTR.D STPTR.W STPTR.D267 PRELD PRELDX268 2696. Atomic Operation Instructions::270 271 LL.W SC.W LL.D SC.D272 AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D273 AMMAX.W AMMAX.D AMMIN.W AMMIN.D274 2757. Barrier Instructions::276 277 IBAR DBAR278 2798. Special Instructions::280 281 SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D282 ASRTLE.D ASRTGT.D283 2849. Privileged Instructions::285 286 CSRRD CSRWR CSRXCHG287 IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D288 CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE289 290Virtual Memory291==============292 293LoongArch supports direct-mapped virtual memory and page-mapped virtual memory.294 295Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple296relationship between virtual address (VA) and physical address (PA)::297 298 VA = PA + FixedOffset299 300Page-mapped virtual memory has arbitrary relationship between VA and PA, which301is recorded in TLB and page tables. LoongArch's TLB includes a fully-associative302MTLB (Multiple Page Size TLB) and set-associative STLB (Single Page Size TLB).303 304By default, the whole virtual address space of LA32 is configured like this:305 306============ =========================== =============================307Name Address Range Attributes308============ =========================== =============================309``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` Page-mapped, Cached, PLV0~3310``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` Direct-mapped, Uncached, PLV0311``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` Direct-mapped, Cached, PLV0312``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` Page-mapped, Cached, PLV0313============ =========================== =============================314 315User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and316KPRANGE1, PA is equal to VA with bit30~31 cleared. For example, the uncached317direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped318VA of 0x00001000 is 0xA0001000.319 320By default, the whole virtual address space of LA64 is configured like this:321 322============ ====================== ======================================323Name Address Range Attributes324============ ====================== ======================================325``XUVRANGE`` ``0x0000000000000000 - Page-mapped, Cached, PLV0~3326 0x3FFFFFFFFFFFFFFF``327``XSPRANGE`` ``0x4000000000000000 - Direct-mapped, Cached / Uncached, PLV0328 0x7FFFFFFFFFFFFFFF``329``XKPRANGE`` ``0x8000000000000000 - Direct-mapped, Cached / Uncached, PLV0330 0xBFFFFFFFFFFFFFFF``331``XKVRANGE`` ``0xC000000000000000 - Page-mapped, Cached, PLV0332 0xFFFFFFFFFFFFFFFF``333============ ====================== ======================================334 335User mode (PLV3) can only access XUVRANGE. For direct-mapped XSPRANGE and336XKPRANGE, PA is equal to VA with bits 60~63 cleared, and the cache attribute337is configured by bits 60~61 in VA: 0 is for strongly-ordered uncached, 1 is338for coherent cached, and 2 is for weakly-ordered uncached.339 340Currently we only use XKPRANGE for direct mapping and XSPRANGE is reserved.341 342To put this in action: the strongly-ordered uncached direct-mapped VA (in343XKPRANGE) of 0x00000000_00001000 is 0x80000000_00001000, the coherent cached344direct-mapped VA (in XKPRANGE) of 0x00000000_00001000 is 0x90000000_00001000,345and the weakly-ordered uncached direct-mapped VA (in XKPRANGE) of 0x00000000346_00001000 is 0xA0000000_00001000.347 348Relationship of Loongson and LoongArch349======================================350 351LoongArch is a RISC ISA which is different from any other existing ones, while352Loongson is a family of processors. Loongson includes 3 series: Loongson-1 is353the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series,354and Loongson-3 is the high-end 64-bit processor series. Old Loongson is based on355MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example:356Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson-3573A5000 (and future revisions) are all based on LoongArch.358 359.. _loongarch-references:360 361References362==========363 364Official web site of Loongson Technology Corp. Ltd.:365 366 http://www.loongson.cn/367 368Developer web site of Loongson and LoongArch (Software and Documentation):369 370 http://www.loongnix.cn/371 372 https://github.com/loongson/373 374 https://loongson.github.io/LoongArch-Documentation/375 376Documentation of LoongArch ISA:377 378 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.10-CN.pdf (in Chinese)379 380 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.10-EN.pdf (in English)381 382Documentation of LoongArch ELF psABI:383 384 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.01-CN.pdf (in Chinese)385 386 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.01-EN.pdf (in English)387 388Linux kernel repository of Loongson and LoongArch:389 390 https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git391