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1================================2Register Usage for Linux/PA-RISC3================================4 5[ an asterisk is used for planned usage which is currently unimplemented ]6 7General Registers as specified by ABI8=====================================9 10Control Registers11-----------------12 13=============================== ===============================================14CR 0 (Recovery Counter) used for ptrace15CR 1-CR 7(undefined) unused16CR 8 (Protection ID) per-process value*17CR 9, 12, 13 (PIDS) unused18CR10 (CCR) lazy FPU saving*19CR11 as specified by ABI (SAR)20CR14 (interruption vector) initialized to fault_vector21CR15 (EIEM) initialized to all ones*22CR16 (Interval Timer) read for cycle count/write starts Interval Tmr23CR17-CR22 interruption parameters24CR19 Interrupt Instruction Register25CR20 Interrupt Space Register26CR21 Interrupt Offset Register27CR22 Interrupt PSW28CR23 (EIRR) read for pending interrupts/write clears bits29CR24 (TR 0) Kernel Space Page Directory Pointer30CR25 (TR 1) User Space Page Directory Pointer31CR26 (TR 2) not used32CR27 (TR 3) Thread descriptor pointer33CR28 (TR 4) not used34CR29 (TR 5) not used35CR30 (TR 6) current / 036CR31 (TR 7) Temporary register, used in various places37=============================== ===============================================38 39Space Registers (kernel mode)40-----------------------------41 42=============================== ===============================================43SR0 temporary space register44SR4-SR7 set to 045SR1 temporary space register46SR2 kernel should not clobber this47SR3 used for userspace accesses (current process)48=============================== ===============================================49 50Space Registers (user mode)51---------------------------52 53=============================== ===============================================54SR0 temporary space register55SR1 temporary space register56SR2 holds space of linux gateway page57SR3 holds user address space value while in kernel58SR4-SR7 Defines short address space for user/kernel59=============================== ===============================================60 61 62Processor Status Word63---------------------64 65=============================== ===============================================66W (64-bit addresses) 067E (Little-endian) 068S (Secure Interval Timer) 069T (Taken Branch Trap) 070H (Higher-privilege trap) 071L (Lower-privilege trap) 072N (Nullify next instruction) used by C code73X (Data memory break disable) 074B (Taken Branch) used by C code75C (code address translation) 1, 0 while executing real-mode code76V (divide step correction) used by C code77M (HPMC mask) 0, 1 while executing HPMC handler*78C/B (carry/borrow bits) used by C code79O (ordered references) 1*80F (performance monitor) 081R (Recovery Counter trap) 082Q (collect interruption state) 1 (0 in code directly preceding an rfi)83P (Protection Identifiers) 1*84D (Data address translation) 1, 0 while executing real-mode code85I (external interrupt mask) used by cli()/sti() macros86=============================== ===============================================87 88"Invisible" Registers89---------------------90 91=============================== ===============================================92PSW default W value 093PSW default E value 094Shadow Registers used by interruption handler code95TOC enable bit 196=============================== ===============================================97 98-------------------------------------------------------------------------99 100The PA-RISC architecture defines 7 registers as "shadow registers".101Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce102the state save and restore time by eliminating the need for general register103(GR) saves and restores in interruption handlers.104Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25.105 106-------------------------------------------------------------------------107 108Register usage notes, originally from John Marvin, with some additional109notes from Randolph Chung.110 111For the general registers:112 113r1,r2,r19-r26,r28,r29 & r31 can be used without saving them first. And of114course, you need to save them if you care about them, before calling115another procedure. Some of the above registers do have special meanings116that you should be aware of:117 118 r1:119 The addil instruction is hardwired to place its result in r1,120 so if you use that instruction be aware of that.121 122 r2:123 This is the return pointer. In general you don't want to124 use this, since you need the pointer to get back to your125 caller. However, it is grouped with this set of registers126 since the caller can't rely on the value being the same127 when you return, i.e. you can copy r2 to another register128 and return through that register after trashing r2, and129 that should not cause a problem for the calling routine.130 131 r19-r22:132 these are generally regarded as temporary registers.133 Note that in 64 bit they are arg7-arg4.134 135 r23-r26:136 these are arg3-arg0, i.e. you can use them if you137 don't care about the values that were passed in anymore.138 139 r28,r29:140 are ret0 and ret1. They are what you pass return values141 in. r28 is the primary return. When returning small structures142 r29 may also be used to pass data back to the caller.143 144 r30:145 stack pointer146 147 r31:148 the ble instruction puts the return pointer in here.149 150 151 r3-r18,r27,r30 need to be saved and restored. r3-r18 are just152 general purpose registers. r27 is the data pointer, and is153 used to make references to global variables easier. r30 is154 the stack pointer.155