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1.. _elf_hwcaps_powerpc:2 3==================4POWERPC ELF HWCAPs5==================6 7This document describes the usage and semantics of the powerpc ELF HWCAPs.8 9 101. Introduction11---------------12 13Some hardware or software features are only available on some CPU14implementations, and/or with certain kernel configurations, but have no other15discovery mechanism available to userspace code. The kernel exposes the16presence of these features to userspace through a set of flags called HWCAPs,17exposed in the auxiliary vector.18 19Userspace software can test for features by acquiring the AT_HWCAP or20AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant21flags are set, e.g.::22 23 bool floating_point_is_present(void)24 {25 unsigned long HWCAPs = getauxval(AT_HWCAP);26 if (HWCAPs & PPC_FEATURE_HAS_FPU)27 return true;28 29 return false;30 }31 32Where software relies on a feature described by a HWCAP, it should check the33relevant HWCAP flag to verify that the feature is present before attempting to34make use of the feature.35 36HWCAP is the preferred method to test for the presence of a feature rather37than probing through other means, which may not be reliable or may cause38unpredictable behaviour.39 40Software that targets a particular platform does not necessarily have to41test for required or implied features. For example if the program requires42FPU, VMX, VSX, it is not necessary to test those HWCAPs, and it may be43impossible to do so if the compiler generates code requiring those features.44 452. Facilities46-------------47 48The Power ISA uses the term "facility" to describe a class of instructions,49registers, interrupts, etc. The presence or absence of a facility indicates50whether this class is available to be used, but the specifics depend on the51ISA version. For example, if the VSX facility is available, the VSX52instructions that can be used differ between the v3.0B and v3.1B ISA53versions.54 553. Categories56-------------57 58The Power ISA before v3.0 uses the term "category" to describe certain59classes of instructions and operating modes which may be optional or60mutually exclusive, the exact meaning of the HWCAP flag may depend on61context, e.g., the presence of the BOOKE feature implies that the server62category is not implemented.63 644. HWCAP allocation65-------------------66 67HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI68Specification (which will be reflected in the kernel's uapi headers).69 705. The HWCAPs exposed in AT_HWCAP71---------------------------------72 73PPC_FEATURE_3274 32-bit CPU75 76PPC_FEATURE_6477 64-bit CPU (userspace may be running in 32-bit mode).78 79PPC_FEATURE_601_INSTR80 The processor is PowerPC 601.81 Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")82 83PPC_FEATURE_HAS_ALTIVEC84 Vector (aka Altivec, VMX) facility is available.85 86PPC_FEATURE_HAS_FPU87 Floating point facility is available.88 89PPC_FEATURE_HAS_MMU90 Memory management unit is present and enabled.91 92PPC_FEATURE_HAS_4xxMAC93 The processor is 40x or 44x family.94 Unused in the kernel since 732b32daef80 ("powerpc: Remove core support for 40x")95 96PPC_FEATURE_UNIFIED_CACHE97 The processor has a unified L1 cache for instructions and data, as98 found in NXP e200.99 Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")100 101PPC_FEATURE_HAS_SPE102 Signal Processing Engine facility is available.103 104PPC_FEATURE_HAS_EFP_SINGLE105 Embedded Floating Point single precision operations are available.106 107PPC_FEATURE_HAS_EFP_DOUBLE108 Embedded Floating Point double precision operations are available.109 110PPC_FEATURE_NO_TB111 The timebase facility (mftb instruction) is not available.112 This is a 601 specific HWCAP, so if it is known that the processor113 running is not a 601, via other HWCAPs or other means, it is not114 required to test this bit before using the timebase.115 Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")116 117PPC_FEATURE_POWER4118 The processor is POWER4 or PPC970/FX/MP.119 POWER4 support dropped from the kernel since 471d7ff8b51b ("powerpc/64s: Remove POWER4 support")120 121PPC_FEATURE_POWER5122 The processor is POWER5.123 124PPC_FEATURE_POWER5_PLUS125 The processor is POWER5+.126 127PPC_FEATURE_CELL128 The processor is Cell.129 130PPC_FEATURE_BOOKE131 The processor implements the embedded category ("BookE") architecture.132 133PPC_FEATURE_SMT134 The processor implements SMT.135 136PPC_FEATURE_ICACHE_SNOOP137 The processor icache is coherent with the dcache, and instruction storage138 can be made consistent with data storage for the purpose of executing139 instructions with the sequence (as described in, e.g., POWER9 Processor140 User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi))::141 142 sync143 icbi (to any address)144 isync145 146PPC_FEATURE_ARCH_2_05147 The processor supports the v2.05 userlevel architecture. Processors148 supporting later architectures DO NOT set this feature.149 150PPC_FEATURE_PA6T151 The processor is PA6T.152 153PPC_FEATURE_HAS_DFP154 DFP facility is available.155 156PPC_FEATURE_POWER6_EXT157 The processor is POWER6.158 159PPC_FEATURE_ARCH_2_06160 The processor supports the v2.06 userlevel architecture. Processors161 supporting later architectures also set this feature.162 163PPC_FEATURE_HAS_VSX164 VSX facility is available.165 166PPC_FEATURE_PSERIES_PERFMON_COMPAT167 The processor supports architected PMU events in the range 0xE0-0xFF.168 169PPC_FEATURE_TRUE_LE170 The processor supports true little-endian mode.171 172PPC_FEATURE_PPC_LE173 The processor supports "PowerPC Little-Endian", that uses address174 munging to make storage access appear to be little-endian, but the175 data is stored in a different format that is unsuitable to be176 accessed by other agents not running in this mode.177 1786. The HWCAPs exposed in AT_HWCAP2179----------------------------------180 181PPC_FEATURE2_ARCH_2_07182 The processor supports the v2.07 userlevel architecture. Processors183 supporting later architectures also set this feature.184 185PPC_FEATURE2_HTM186 Transactional Memory feature is available.187 188PPC_FEATURE2_DSCR189 DSCR facility is available.190 191PPC_FEATURE2_EBB192 EBB facility is available.193 194PPC_FEATURE2_ISEL195 isel instruction is available. This is superseded by ARCH_2_07 and196 later.197 198PPC_FEATURE2_TAR199 TAR facility is available.200 201PPC_FEATURE2_VEC_CRYPTO202 v2.07 crypto instructions are available.203 204PPC_FEATURE2_HTM_NOSC205 System calls fail if called in a transactional state, see206 Documentation/arch/powerpc/syscall64-abi.rst207 208PPC_FEATURE2_ARCH_3_00209 The processor supports the v3.0B / v3.0C userlevel architecture. Processors210 supporting later architectures also set this feature.211 212PPC_FEATURE2_HAS_IEEE128213 IEEE 128-bit binary floating point is supported with VSX214 quad-precision instructions and data types.215 216PPC_FEATURE2_DARN217 darn instruction is available.218 219PPC_FEATURE2_SCV220 The scv 0 instruction may be used for system calls, see221 Documentation/arch/powerpc/syscall64-abi.rst.222 223PPC_FEATURE2_HTM_NO_SUSPEND224 A limited Transactional Memory facility that does not support suspend is225 available, see Documentation/arch/powerpc/transactional_memory.rst.226 227PPC_FEATURE2_ARCH_3_1228 The processor supports the v3.1 userlevel architecture. Processors229 supporting later architectures also set this feature.230 231PPC_FEATURE2_MMA232 MMA facility is available.233