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1.. SPDX-License-Identifier: GPL-2.02 3TSX Async Abort (TAA) mitigation4================================5 6.. _tsx_async_abort:7 8Overview9--------10 11TSX Async Abort (TAA) is a side channel attack on internal buffers in some12Intel processors similar to Microachitectural Data Sampling (MDS). In this13case certain loads may speculatively pass invalid data to dependent operations14when an asynchronous abort condition is pending in a Transactional15Synchronization Extensions (TSX) transaction. This includes loads with no16fault or assist condition. Such loads may speculatively expose stale data from17the same uarch data structures as in MDS, with same scope of exposure i.e.18same-thread and cross-thread. This issue affects all current processors that19support TSX.20 21Mitigation strategy22-------------------23 24a) TSX disable - one of the mitigations is to disable TSX. A new MSR25IA32_TSX_CTRL will be available in future and current processors after26microcode update which can be used to disable TSX. In addition, it27controls the enumeration of the TSX feature bits (RTM and HLE) in CPUID.28 29b) Clear CPU buffers - similar to MDS, clearing the CPU buffers mitigates this30vulnerability. More details on this approach can be found in31:ref:`Documentation/admin-guide/hw-vuln/mds.rst <mds>`.32 33Kernel internal mitigation modes34--------------------------------35 36 ============= ============================================================37 off Mitigation is disabled. Either the CPU is not affected or38 tsx_async_abort=off is supplied on the kernel command line.39 40 tsx disabled Mitigation is enabled. TSX feature is disabled by default at41 bootup on processors that support TSX control.42 43 verw Mitigation is enabled. CPU is affected and MD_CLEAR is44 advertised in CPUID.45 46 ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not47 advertised in CPUID. That is mainly for virtualization48 scenarios where the host has the updated microcode but the49 hypervisor does not expose MD_CLEAR in CPUID. It's a best50 effort approach without guarantee.51 ============= ============================================================52 53If the CPU is affected and the "tsx_async_abort" kernel command line parameter is54not provided then the kernel selects an appropriate mitigation depending on the55status of RTM and MD_CLEAR CPUID bits.56 57Below tables indicate the impact of tsx=on|off|auto cmdline options on state of58TAA mitigation, VERW behavior and TSX feature for various combinations of59MSR_IA32_ARCH_CAPABILITIES bits.60 611. "tsx=off"62 63========= ========= ============ ============ ============== =================== ======================64MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=off65---------------------------------- -------------------------------------------------------------------------66TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation67 after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full68========= ========= ============ ============ ============== =================== ======================69 0 0 0 HW default Yes Same as MDS Same as MDS70 0 0 1 Invalid case Invalid case Invalid case Invalid case71 0 1 0 HW default No Need ucode update Need ucode update72 0 1 1 Disabled Yes TSX disabled TSX disabled73 1 X 1 Disabled X None needed None needed74========= ========= ============ ============ ============== =================== ======================75 762. "tsx=on"77 78========= ========= ============ ============ ============== =================== ======================79MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=on80---------------------------------- -------------------------------------------------------------------------81TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation82 after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full83========= ========= ============ ============ ============== =================== ======================84 0 0 0 HW default Yes Same as MDS Same as MDS85 0 0 1 Invalid case Invalid case Invalid case Invalid case86 0 1 0 HW default No Need ucode update Need ucode update87 0 1 1 Enabled Yes None Same as MDS88 1 X 1 Enabled X None needed None needed89========= ========= ============ ============ ============== =================== ======================90 913. "tsx=auto"92 93========= ========= ============ ============ ============== =================== ======================94MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=auto95---------------------------------- -------------------------------------------------------------------------96TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation97 after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full98========= ========= ============ ============ ============== =================== ======================99 0 0 0 HW default Yes Same as MDS Same as MDS100 0 0 1 Invalid case Invalid case Invalid case Invalid case101 0 1 0 HW default No Need ucode update Need ucode update102 0 1 1 Disabled Yes TSX disabled TSX disabled103 1 X 1 Enabled X None needed None needed104========= ========= ============ ============ ============== =================== ======================105 106In the tables, TSX_CTRL_MSR is a new bit in MSR_IA32_ARCH_CAPABILITIES that107indicates whether MSR_IA32_TSX_CTRL is supported.108 109There are two control bits in IA32_TSX_CTRL MSR:110 111 Bit 0: When set it disables the Restricted Transactional Memory (RTM)112 sub-feature of TSX (will force all transactions to abort on the113 XBEGIN instruction).114 115 Bit 1: When set it disables the enumeration of the RTM and HLE feature116 (i.e. it will make CPUID(EAX=7).EBX{bit4} and117 CPUID(EAX=7).EBX{bit11} read as 0).118