52 lines · plain
1===========================================2Atomic Operation Control (ATOMCTL) Register3===========================================4 5We Have Atomic Operation Control (ATOMCTL) Register.6This register determines the effect of using a S32C1I instruction7with various combinations of:8 9 1. With and without an Coherent Cache Controller which10 can do Atomic Transactions to the memory internally.11 12 2. With and without An Intelligent Memory Controller which13 can do Atomic Transactions itself.14 15The Core comes up with a default value of for the three types of cache ops::16 17 0x28: (WB: Internal, WT: Internal, BY:Exception)18 19On the FPGA Cards we typically simulate an Intelligent Memory controller20which can implement RCW transactions. For FPGA cards with an External21Memory controller we let it to the atomic operations internally while22doing a Cached (WB) transaction and use the Memory RCW for un-cached23operations.24 25For systems without an coherent cache controller, non-MX, we always26use the memory controllers RCW, though non-MX controllers likely27support the Internal Operation.28 29CUSTOMER-WARNING:30 Virtually all customers buy their memory controllers from vendors that31 don't support atomic RCW memory transactions and will likely want to32 configure this register to not use RCW.33 34Developers might find using RCW in Bypass mode convenient when testing35with the cache being bypassed; for example studying cache alias problems.36 37See Section 4.3.12.4 of ISA; Bits::38 39 WB WT BY40 5 4 | 3 2 | 1 041 42========= ================== ================== ===============43 2 Bit44 Field45 Values WB - Write Back WT - Write Thru BY - Bypass46========= ================== ================== ===============47 0 Exception Exception Exception48 1 RCW Transaction RCW Transaction RCW Transaction49 2 Internal Operation Internal Operation Reserved50 3 Reserved Reserved Reserved51========= ================== ================== ===============52