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1.. contents::2.. sectnum::3 4======================================5BPF Instruction Set Architecture (ISA)6======================================7 8eBPF, also commonly9referred to as BPF, is a technology with origins in the Linux kernel10that can run untrusted programs in a privileged context such as an11operating system kernel. This document specifies the BPF instruction12set architecture (ISA).13 14As a historical note, BPF originally stood for Berkeley Packet Filter,15but now that it can do so much more than packet filtering, the acronym16no longer makes sense. BPF is now considered a standalone term that17does not stand for anything. The original BPF is sometimes referred to18as cBPF (classic BPF) to distinguish it from the now widely deployed19eBPF (extended BPF).20 21Documentation conventions22=========================23 24The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT",25"SHOULD", "SHOULD NOT", "RECOMMENDED", "NOT RECOMMENDED", "MAY", and26"OPTIONAL" in this document are to be interpreted as described in27BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_28`<https://www.rfc-editor.org/info/rfc8174>`_29when, and only when, they appear in all capitals, as shown here.30 31For brevity and consistency, this document refers to families32of types using a shorthand syntax and refers to several expository,33mnemonic functions when describing the semantics of instructions.34The range of valid values for those types and the semantics of those35functions are defined in the following subsections.36 37Types38-----39This document refers to integer types with the notation `SN` to specify40a type's signedness (`S`) and bit width (`N`), respectively.41 42.. table:: Meaning of signedness notation43 44 ==== =========45 S Meaning46 ==== =========47 u unsigned48 s signed49 ==== =========50 51.. table:: Meaning of bit-width notation52 53 ===== =========54 N Bit width55 ===== =========56 8 8 bits57 16 16 bits58 32 32 bits59 64 64 bits60 128 128 bits61 ===== =========62 63For example, `u32` is a type whose valid values are all the 32-bit unsigned64numbers and `s16` is a type whose valid values are all the 16-bit signed65numbers.66 67Functions68---------69 70The following byteswap functions are direction-agnostic. That is,71the same function is used for conversion in either direction discussed72below.73 74* be16: Takes an unsigned 16-bit number and converts it between75 host byte order and big-endian76 (`IEN137 <https://www.rfc-editor.org/ien/ien137.txt>`_) byte order.77* be32: Takes an unsigned 32-bit number and converts it between78 host byte order and big-endian byte order.79* be64: Takes an unsigned 64-bit number and converts it between80 host byte order and big-endian byte order.81* bswap16: Takes an unsigned 16-bit number in either big- or little-endian82 format and returns the equivalent number with the same bit width but83 opposite endianness.84* bswap32: Takes an unsigned 32-bit number in either big- or little-endian85 format and returns the equivalent number with the same bit width but86 opposite endianness.87* bswap64: Takes an unsigned 64-bit number in either big- or little-endian88 format and returns the equivalent number with the same bit width but89 opposite endianness.90* le16: Takes an unsigned 16-bit number and converts it between91 host byte order and little-endian byte order.92* le32: Takes an unsigned 32-bit number and converts it between93 host byte order and little-endian byte order.94* le64: Takes an unsigned 64-bit number and converts it between95 host byte order and little-endian byte order.96 97Definitions98-----------99 100.. glossary::101 102 Sign Extend103 To `sign extend an` ``X`` `-bit number, A, to a` ``Y`` `-bit number, B ,` means to104 105 #. Copy all ``X`` bits from `A` to the lower ``X`` bits of `B`.106 #. Set the value of the remaining ``Y`` - ``X`` bits of `B` to the value of107 the most-significant bit of `A`.108 109.. admonition:: Example110 111 Sign extend an 8-bit number ``A`` to a 16-bit number ``B`` on a big-endian platform:112 ::113 114 A: 10000110115 B: 11111111 10000110116 117Conformance groups118------------------119 120An implementation does not need to support all instructions specified in this121document (e.g., deprecated instructions). Instead, a number of conformance122groups are specified. An implementation MUST support the base32 conformance123group and MAY support additional conformance groups, where supporting a124conformance group means it MUST support all instructions in that conformance125group.126 127The use of named conformance groups enables interoperability between a runtime128that executes instructions, and tools such as compilers that generate129instructions for the runtime. Thus, capability discovery in terms of130conformance groups might be done manually by users or automatically by tools.131 132Each conformance group has a short ASCII label (e.g., "base32") that133corresponds to a set of instructions that are mandatory. That is, each134instruction has one or more conformance groups of which it is a member.135 136This document defines the following conformance groups:137 138* base32: includes all instructions defined in this139 specification unless otherwise noted.140* base64: includes base32, plus instructions explicitly noted141 as being in the base64 conformance group.142* atomic32: includes 32-bit atomic operation instructions (see `Atomic operations`_).143* atomic64: includes atomic32, plus 64-bit atomic operation instructions.144* divmul32: includes 32-bit division, multiplication, and modulo instructions.145* divmul64: includes divmul32, plus 64-bit division, multiplication,146 and modulo instructions.147* packet: deprecated packet access instructions.148 149Instruction encoding150====================151 152BPF has two instruction encodings:153 154* the basic instruction encoding, which uses 64 bits to encode an instruction155* the wide instruction encoding, which appends a second 64 bits156 after the basic instruction for a total of 128 bits.157 158Basic instruction encoding159--------------------------160 161A basic instruction is encoded as follows::162 163 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+164 | opcode | regs | offset |165 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+166 | imm |167 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+168 169**opcode**170 operation to perform, encoded as follows::171 172 +-+-+-+-+-+-+-+-+173 |specific |class|174 +-+-+-+-+-+-+-+-+175 176 **specific**177 The format of these bits varies by instruction class178 179 **class**180 The instruction class (see `Instruction classes`_)181 182**regs**183 The source and destination register numbers, encoded as follows184 on a little-endian host::185 186 +-+-+-+-+-+-+-+-+187 |src_reg|dst_reg|188 +-+-+-+-+-+-+-+-+189 190 and as follows on a big-endian host::191 192 +-+-+-+-+-+-+-+-+193 |dst_reg|src_reg|194 +-+-+-+-+-+-+-+-+195 196 **src_reg**197 the source register number (0-10), except where otherwise specified198 (`64-bit immediate instructions`_ reuse this field for other purposes)199 200 **dst_reg**201 destination register number (0-10), unless otherwise specified202 (future instructions might reuse this field for other purposes)203 204**offset**205 signed integer offset used with pointer arithmetic, except where206 otherwise specified (some arithmetic instructions reuse this field207 for other purposes)208 209**imm**210 signed integer immediate value211 212Note that the contents of multi-byte fields ('offset' and 'imm') are213stored using big-endian byte ordering on big-endian hosts and214little-endian byte ordering on little-endian hosts.215 216For example::217 218 opcode offset imm assembly219 src_reg dst_reg220 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little221 dst_reg src_reg222 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big223 224Note that most instructions do not use all of the fields.225Unused fields SHALL be cleared to zero.226 227Wide instruction encoding228--------------------------229 230Some instructions are defined to use the wide instruction encoding,231which uses two 32-bit immediate values. The 64 bits following232the basic instruction format contain a pseudo instruction233with 'opcode', 'dst_reg', 'src_reg', and 'offset' all set to zero.234 235This is depicted in the following figure::236 237 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+238 | opcode | regs | offset |239 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+240 | imm |241 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+242 | reserved |243 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+244 | next_imm |245 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+246 247**opcode**248 operation to perform, encoded as explained above249 250**regs**251 The source and destination register numbers (unless otherwise252 specified), encoded as explained above253 254**offset**255 signed integer offset used with pointer arithmetic, unless256 otherwise specified257 258**imm**259 signed integer immediate value260 261**reserved**262 unused, set to zero263 264**next_imm**265 second signed integer immediate value266 267Instruction classes268-------------------269 270The three least significant bits of the 'opcode' field store the instruction class:271 272.. table:: Instruction class273 274 ===== ===== =============================== ===================================275 class value description reference276 ===== ===== =============================== ===================================277 LD 0x0 non-standard load operations `Load and store instructions`_278 LDX 0x1 load into register operations `Load and store instructions`_279 ST 0x2 store from immediate operations `Load and store instructions`_280 STX 0x3 store from register operations `Load and store instructions`_281 ALU 0x4 32-bit arithmetic operations `Arithmetic and jump instructions`_282 JMP 0x5 64-bit jump operations `Arithmetic and jump instructions`_283 JMP32 0x6 32-bit jump operations `Arithmetic and jump instructions`_284 ALU64 0x7 64-bit arithmetic operations `Arithmetic and jump instructions`_285 ===== ===== =============================== ===================================286 287Arithmetic and jump instructions288================================289 290For arithmetic and jump instructions (``ALU``, ``ALU64``, ``JMP`` and291``JMP32``), the 8-bit 'opcode' field is divided into three parts::292 293 +-+-+-+-+-+-+-+-+294 | code |s|class|295 +-+-+-+-+-+-+-+-+296 297**code**298 the operation code, whose meaning varies by instruction class299 300**s (source)**301 the source operand location, which unless otherwise specified is one of:302 303 .. table:: Source operand location304 305 ====== ===== ==============================================306 source value description307 ====== ===== ==============================================308 K 0 use 32-bit 'imm' value as source operand309 X 1 use 'src_reg' register value as source operand310 ====== ===== ==============================================311 312**instruction class**313 the instruction class (see `Instruction classes`_)314 315Arithmetic instructions316-----------------------317 318``ALU`` uses 32-bit wide operands while ``ALU64`` uses 64-bit wide operands for319otherwise identical operations. ``ALU64`` instructions belong to the320base64 conformance group unless noted otherwise.321The 'code' field encodes the operation as below, where 'src' refers to the322the source operand and 'dst' refers to the value of the destination323register.324 325.. table:: Arithmetic instructions326 327 ===== ===== ======= ==========================================================328 name code offset description329 ===== ===== ======= ==========================================================330 ADD 0x0 0 dst += src331 SUB 0x1 0 dst -= src332 MUL 0x2 0 dst \*= src333 DIV 0x3 0 dst = (src != 0) ? (dst / src) : 0334 SDIV 0x3 1 dst = (src != 0) ? (dst s/ src) : 0335 OR 0x4 0 dst \|= src336 AND 0x5 0 dst &= src337 LSH 0x6 0 dst <<= (src & mask)338 RSH 0x7 0 dst >>= (src & mask)339 NEG 0x8 0 dst = -dst340 MOD 0x9 0 dst = (src != 0) ? (dst % src) : dst341 SMOD 0x9 1 dst = (src != 0) ? (dst s% src) : dst342 XOR 0xa 0 dst ^= src343 MOV 0xb 0 dst = src344 MOVSX 0xb 8/16/32 dst = (s8,s16,s32)src345 ARSH 0xc 0 :term:`sign extending<Sign Extend>` dst >>= (src & mask)346 END 0xd 0 byte swap operations (see `Byte swap instructions`_ below)347 ===== ===== ======= ==========================================================348 349Underflow and overflow are allowed during arithmetic operations, meaning350the 64-bit or 32-bit value will wrap. If BPF program execution would351result in division by zero, the destination register is instead set to zero.352If execution would result in modulo by zero, for ``ALU64`` the value of353the destination register is unchanged whereas for ``ALU`` the upper35432 bits of the destination register are zeroed.355 356``{ADD, X, ALU}``, where 'code' = ``ADD``, 'source' = ``X``, and 'class' = ``ALU``, means::357 358 dst = (u32) ((u32) dst + (u32) src)359 360where '(u32)' indicates that the upper 32 bits are zeroed.361 362``{ADD, X, ALU64}`` means::363 364 dst = dst + src365 366``{XOR, K, ALU}`` means::367 368 dst = (u32) dst ^ (u32) imm369 370``{XOR, K, ALU64}`` means::371 372 dst = dst ^ imm373 374Note that most arithmetic instructions have 'offset' set to 0. Only three instructions375(``SDIV``, ``SMOD``, ``MOVSX``) have a non-zero 'offset'.376 377Division, multiplication, and modulo operations for ``ALU`` are part378of the "divmul32" conformance group, and division, multiplication, and379modulo operations for ``ALU64`` are part of the "divmul64" conformance380group.381The division and modulo operations support both unsigned and signed flavors.382 383For unsigned operations (``DIV`` and ``MOD``), for ``ALU``,384'imm' is interpreted as a 32-bit unsigned value. For ``ALU64``,385'imm' is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then386interpreted as a 64-bit unsigned value.387 388For signed operations (``SDIV`` and ``SMOD``), for ``ALU``,389'imm' is interpreted as a 32-bit signed value. For ``ALU64``, 'imm'390is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then391interpreted as a 64-bit signed value.392 393Note that there are varying definitions of the signed modulo operation394when the dividend or divisor are negative, where implementations often395vary by language such that Python, Ruby, etc. differ from C, Go, Java,396etc. This specification requires that signed modulo MUST use truncated division397(where -13 % 3 == -1) as implemented in C, Go, etc.::398 399 a % n = a - n * trunc(a / n)400 401The ``MOVSX`` instruction does a move operation with sign extension.402``{MOVSX, X, ALU}`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into40332-bit operands, and zeroes the remaining upper 32 bits.404``{MOVSX, X, ALU64}`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit405operands into 64-bit operands. Unlike other arithmetic instructions,406``MOVSX`` is only defined for register source operands (``X``).407 408``{MOV, K, ALU64}`` means::409 410 dst = (s64)imm411 412``{MOV, X, ALU}`` means::413 414 dst = (u32)src415 416``{MOVSX, X, ALU}`` with 'offset' 8 means::417 418 dst = (u32)(s32)(s8)src419 420 421The ``NEG`` instruction is only defined when the source bit is clear422(``K``).423 424Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31)425for 32-bit operations.426 427Byte swap instructions428----------------------429 430The byte swap instructions use instruction classes of ``ALU`` and ``ALU64``431and a 4-bit 'code' field of ``END``.432 433The byte swap instructions operate on the destination register434only and do not use a separate source register or immediate value.435 436For ``ALU``, the 1-bit source operand field in the opcode is used to437select what byte order the operation converts from or to. For438``ALU64``, the 1-bit source operand field in the opcode is reserved439and MUST be set to 0.440 441.. table:: Byte swap instructions442 443 ===== ======== ===== =================================================444 class source value description445 ===== ======== ===== =================================================446 ALU LE 0 convert between host byte order and little endian447 ALU BE 1 convert between host byte order and big endian448 ALU64 Reserved 0 do byte swap unconditionally449 ===== ======== ===== =================================================450 451The 'imm' field encodes the width of the swap operations. The following widths452are supported: 16, 32 and 64. Width 64 operations belong to the base64453conformance group and other swap operations belong to the base32454conformance group.455 456Examples:457 458``{END, LE, ALU}`` with 'imm' = 16/32/64 means::459 460 dst = le16(dst)461 dst = le32(dst)462 dst = le64(dst)463 464``{END, BE, ALU}`` with 'imm' = 16/32/64 means::465 466 dst = be16(dst)467 dst = be32(dst)468 dst = be64(dst)469 470``{END, TO, ALU64}`` with 'imm' = 16/32/64 means::471 472 dst = bswap16(dst)473 dst = bswap32(dst)474 dst = bswap64(dst)475 476Jump instructions477-----------------478 479``JMP32`` uses 32-bit wide operands and indicates the base32480conformance group, while ``JMP`` uses 64-bit wide operands for481otherwise identical operations, and indicates the base64 conformance482group unless otherwise specified.483The 'code' field encodes the operation as below:484 485.. table:: Jump instructions486 487 ======== ===== ======= ================================= ===================================================488 code value src_reg description notes489 ======== ===== ======= ================================= ===================================================490 JA 0x0 0x0 PC += offset {JA, K, JMP} only491 JA 0x0 0x0 PC += imm {JA, K, JMP32} only492 JEQ 0x1 any PC += offset if dst == src493 JGT 0x2 any PC += offset if dst > src unsigned494 JGE 0x3 any PC += offset if dst >= src unsigned495 JSET 0x4 any PC += offset if dst & src496 JNE 0x5 any PC += offset if dst != src497 JSGT 0x6 any PC += offset if dst > src signed498 JSGE 0x7 any PC += offset if dst >= src signed499 CALL 0x8 0x0 call helper function by static ID {CALL, K, JMP} only, see `Helper functions`_500 CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-local functions`_501 CALL 0x8 0x2 call helper function by BTF ID {CALL, K, JMP} only, see `Helper functions`_502 EXIT 0x9 0x0 return {CALL, K, JMP} only503 JLT 0xa any PC += offset if dst < src unsigned504 JLE 0xb any PC += offset if dst <= src unsigned505 JSLT 0xc any PC += offset if dst < src signed506 JSLE 0xd any PC += offset if dst <= src signed507 ======== ===== ======= ================================= ===================================================508 509where 'PC' denotes the program counter, and the offset to increment by510is in units of 64-bit instructions relative to the instruction following511the jump instruction. Thus 'PC += 1' skips execution of the next512instruction if it's a basic instruction or results in undefined behavior513if the next instruction is a 128-bit wide instruction.514 515Example:516 517``{JSGE, X, JMP32}`` means::518 519 if (s32)dst s>= (s32)src goto +offset520 521where 's>=' indicates a signed '>=' comparison.522 523``{JLE, K, JMP}`` means::524 525 if dst <= (u64)(s64)imm goto +offset526 527``{JA, K, JMP32}`` means::528 529 gotol +imm530 531where 'imm' means the branch offset comes from the 'imm' field.532 533Note that there are two flavors of ``JA`` instructions. The534``JMP`` class permits a 16-bit jump offset specified by the 'offset'535field, whereas the ``JMP32`` class permits a 32-bit jump offset536specified by the 'imm' field. A > 16-bit conditional jump may be537converted to a < 16-bit conditional jump plus a 32-bit unconditional538jump.539 540All ``CALL`` and ``JA`` instructions belong to the541base32 conformance group.542 543Helper functions544~~~~~~~~~~~~~~~~545 546Helper functions are a concept whereby BPF programs can call into a547set of function calls exposed by the underlying platform.548 549Historically, each helper function was identified by a static ID550encoded in the 'imm' field. Further documentation of helper functions551is outside the scope of this document and standardization is left for552future work, but use is widely deployed and more information can be553found in platform-specific documentation (e.g., Linux kernel documentation).554 555Platforms that support the BPF Type Format (BTF) support identifying556a helper function by a BTF ID encoded in the 'imm' field, where the BTF ID557identifies the helper name and type. Further documentation of BTF558is outside the scope of this document and standardization is left for559future work, but use is widely deployed and more information can be560found in platform-specific documentation (e.g., Linux kernel documentation).561 562Program-local functions563~~~~~~~~~~~~~~~~~~~~~~~564Program-local functions are functions exposed by the same BPF program as the565caller, and are referenced by offset from the instruction following the call566instruction, similar to ``JA``. The offset is encoded in the 'imm' field of567the call instruction. An ``EXIT`` within the program-local function will568return to the caller.569 570Load and store instructions571===========================572 573For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the5748-bit 'opcode' field is divided as follows::575 576 +-+-+-+-+-+-+-+-+577 |mode |sz |class|578 +-+-+-+-+-+-+-+-+579 580**mode**581 The mode modifier is one of:582 583 .. table:: Mode modifier584 585 ============= ===== ==================================== =============586 mode modifier value description reference587 ============= ===== ==================================== =============588 IMM 0 64-bit immediate instructions `64-bit immediate instructions`_589 ABS 1 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_590 IND 2 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_591 MEM 3 regular load and store operations `Regular load and store operations`_592 MEMSX 4 sign-extension load operations `Sign-extension load operations`_593 ATOMIC 6 atomic operations `Atomic operations`_594 ============= ===== ==================================== =============595 596**sz (size)**597 The size modifier is one of:598 599 .. table:: Size modifier600 601 ==== ===== =====================602 size value description603 ==== ===== =====================604 W 0 word (4 bytes)605 H 1 half word (2 bytes)606 B 2 byte607 DW 3 double word (8 bytes)608 ==== ===== =====================609 610 Instructions using ``DW`` belong to the base64 conformance group.611 612**class**613 The instruction class (see `Instruction classes`_)614 615Regular load and store operations616---------------------------------617 618The ``MEM`` mode modifier is used to encode regular load and store619instructions that transfer data between a register and memory.620 621``{MEM, <size>, STX}`` means::622 623 *(size *) (dst + offset) = src624 625``{MEM, <size>, ST}`` means::626 627 *(size *) (dst + offset) = imm628 629``{MEM, <size>, LDX}`` means::630 631 dst = *(unsigned size *) (src + offset)632 633Where '<size>' is one of: ``B``, ``H``, ``W``, or ``DW``, and634'unsigned size' is one of: u8, u16, u32, or u64.635 636Sign-extension load operations637------------------------------638 639The ``MEMSX`` mode modifier is used to encode :term:`sign-extension<Sign Extend>` load640instructions that transfer data between a register and memory.641 642``{MEMSX, <size>, LDX}`` means::643 644 dst = *(signed size *) (src + offset)645 646Where '<size>' is one of: ``B``, ``H``, or ``W``, and647'signed size' is one of: s8, s16, or s32.648 649Atomic operations650-----------------651 652Atomic operations are operations that operate on memory and can not be653interrupted or corrupted by other access to the same memory region654by other BPF programs or means outside of this specification.655 656All atomic operations supported by BPF are encoded as store operations657that use the ``ATOMIC`` mode modifier as follows:658 659* ``{ATOMIC, W, STX}`` for 32-bit operations, which are660 part of the "atomic32" conformance group.661* ``{ATOMIC, DW, STX}`` for 64-bit operations, which are662 part of the "atomic64" conformance group.663* 8-bit and 16-bit wide atomic operations are not supported.664 665The 'imm' field is used to encode the actual atomic operation.666Simple atomic operation use a subset of the values defined to encode667arithmetic operations in the 'imm' field to encode the atomic operation:668 669.. table:: Simple atomic operations670 671 ======== ===== ===========672 imm value description673 ======== ===== ===========674 ADD 0x00 atomic add675 OR 0x40 atomic or676 AND 0x50 atomic and677 XOR 0xa0 atomic xor678 ======== ===== ===========679 680 681``{ATOMIC, W, STX}`` with 'imm' = ADD means::682 683 *(u32 *)(dst + offset) += src684 685``{ATOMIC, DW, STX}`` with 'imm' = ADD means::686 687 *(u64 *)(dst + offset) += src688 689In addition to the simple atomic operations, there also is a modifier and690two complex atomic operations:691 692.. table:: Complex atomic operations693 694 =========== ================ ===========================695 imm value description696 =========== ================ ===========================697 FETCH 0x01 modifier: return old value698 XCHG 0xe0 | FETCH atomic exchange699 CMPXCHG 0xf0 | FETCH atomic compare and exchange700 =========== ================ ===========================701 702The ``FETCH`` modifier is optional for simple atomic operations, and703always set for the complex atomic operations. If the ``FETCH`` flag704is set, then the operation also overwrites ``src`` with the value that705was in memory before it was modified.706 707The ``XCHG`` operation atomically exchanges ``src`` with the value708addressed by ``dst + offset``.709 710The ``CMPXCHG`` operation atomically compares the value addressed by711``dst + offset`` with ``R0``. If they match, the value addressed by712``dst + offset`` is replaced with ``src``. In either case, the713value that was at ``dst + offset`` before the operation is zero-extended714and loaded back to ``R0``.715 71664-bit immediate instructions717-----------------------------718 719Instructions with the ``IMM`` 'mode' modifier use the wide instruction720encoding defined in `Instruction encoding`_, and use the 'src_reg' field of the721basic instruction to hold an opcode subtype.722 723The following table defines a set of ``{IMM, DW, LD}`` instructions724with opcode subtypes in the 'src_reg' field, using new terms such as "map"725defined further below:726 727.. table:: 64-bit immediate instructions728 729 ======= ========================================= =========== ==============730 src_reg pseudocode imm type dst type731 ======= ========================================= =========== ==============732 0x0 dst = (next_imm << 32) | imm integer integer733 0x1 dst = map_by_fd(imm) map fd map734 0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data address735 0x3 dst = var_addr(imm) variable id data address736 0x4 dst = code_addr(imm) integer code address737 0x5 dst = map_by_idx(imm) map index map738 0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data address739 ======= ========================================= =========== ==============740 741where742 743* map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_)744* map_by_idx(imm) means to convert a 32-bit index into an address of a map745* map_val(map) gets the address of the first value in a given map746* var_addr(imm) gets the address of a platform variable (see `Platform Variables`_) with a given id747* code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions748* the 'imm type' can be used by disassemblers for display749* the 'dst type' can be used for verification and JIT compilation purposes750 751Maps752~~~~753 754Maps are shared memory regions accessible by BPF programs on some platforms.755A map can have various semantics as defined in a separate document, and may or756may not have a single contiguous memory region, but the 'map_val(map)' is757currently only defined for maps that do have a single contiguous memory region.758 759Each map can have a file descriptor (fd) if supported by the platform, where760'map_by_fd(imm)' means to get the map with the specified file descriptor. Each761BPF program can also be defined to use a set of maps associated with the762program at load time, and 'map_by_idx(imm)' means to get the map with the given763index in the set associated with the BPF program containing the instruction.764 765Platform Variables766~~~~~~~~~~~~~~~~~~767 768Platform variables are memory regions, identified by integer ids, exposed by769the runtime and accessible by BPF programs on some platforms. The770'var_addr(imm)' operation means to get the address of the memory region771identified by the given id.772 773Legacy BPF Packet access instructions774-------------------------------------775 776BPF previously introduced special instructions for access to packet data that were777carried over from classic BPF. These instructions used an instruction778class of ``LD``, a size modifier of ``W``, ``H``, or ``B``, and a779mode modifier of ``ABS`` or ``IND``. The 'dst_reg' and 'offset' fields were780set to zero, and 'src_reg' was set to zero for ``ABS``. However, these781instructions are deprecated and SHOULD no longer be used. All legacy packet782access instructions belong to the "packet" conformance group.783