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1=========================2Dynamic DMA mapping Guide3=========================4 5:Author: David S. Miller <davem@redhat.com>6:Author: Richard Henderson <rth@cygnus.com>7:Author: Jakub Jelinek <jakub@redhat.com>8 9This is a guide to device driver writers on how to use the DMA API10with example pseudo-code. For a concise description of the API, see11Documentation/core-api/dma-api.rst.12 13CPU and DMA addresses14=====================15 16There are several kinds of addresses involved in the DMA API, and it's17important to understand the differences.18 19The kernel normally uses virtual addresses. Any address returned by20kmalloc(), vmalloc(), and similar interfaces is a virtual address and can21be stored in a ``void *``.22 23The virtual memory system (TLB, page tables, etc.) translates virtual24addresses to CPU physical addresses, which are stored as "phys_addr_t" or25"resource_size_t". The kernel manages device resources like registers as26physical addresses. These are the addresses in /proc/iomem. The physical27address is not directly useful to a driver; it must use ioremap() to map28the space and produce a virtual address.29 30I/O devices use a third kind of address: a "bus address". If a device has31registers at an MMIO address, or if it performs DMA to read or write system32memory, the addresses used by the device are bus addresses. In some33systems, bus addresses are identical to CPU physical addresses, but in34general they are not. IOMMUs and host bridges can produce arbitrary35mappings between physical and bus addresses.36 37From a device's point of view, DMA uses the bus address space, but it may38be restricted to a subset of that space. For example, even if a system39supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU40so devices only need to use 32-bit DMA addresses.41 42Here's a picture and some examples::43 44 CPU CPU Bus45 Virtual Physical Address46 Address Address Space47 Space Space48 49 +-------+ +------+ +------+50 | | |MMIO | Offset | |51 | | Virtual |Space | applied | |52 C +-------+ --------> B +------+ ----------> +------+ A53 | | mapping | | by host | |54 +-----+ | | | | bridge | | +--------+55 | | | | +------+ | | | |56 | CPU | | | | RAM | | | | Device |57 | | | | | | | | | |58 +-----+ +-------+ +------+ +------+ +--------+59 | | Virtual |Buffer| Mapping | |60 X +-------+ --------> Y +------+ <---------- +------+ Z61 | | mapping | RAM | by IOMMU62 | | | |63 | | | |64 +-------+ +------+65 66During the enumeration process, the kernel learns about I/O devices and67their MMIO space and the host bridges that connect them to the system. For68example, if a PCI device has a BAR, the kernel reads the bus address (A)69from the BAR and converts it to a CPU physical address (B). The address B70is stored in a struct resource and usually exposed via /proc/iomem. When a71driver claims a device, it typically uses ioremap() to map physical address72B at a virtual address (C). It can then use, e.g., ioread32(C), to access73the device registers at bus address A.74 75If the device supports DMA, the driver sets up a buffer using kmalloc() or76a similar interface, which returns a virtual address (X). The virtual77memory system maps X to a physical address (Y) in system RAM. The driver78can use virtual address X to access the buffer, but the device itself79cannot because DMA doesn't go through the CPU virtual memory system.80 81In some simple systems, the device can do DMA directly to physical address82Y. But in many others, there is IOMMU hardware that translates DMA83addresses to physical addresses, e.g., it translates Z to Y. This is part84of the reason for the DMA API: the driver can give a virtual address X to85an interface like dma_map_single(), which sets up any required IOMMU86mapping and returns the DMA address Z. The driver then tells the device to87do DMA to Z, and the IOMMU maps it to the buffer at address Y in system88RAM.89 90So that Linux can use the dynamic DMA mapping, it needs some help from the91drivers, namely it has to take into account that DMA addresses should be92mapped only for the time they are actually used and unmapped after the DMA93transfer.94 95The following API will work of course even on platforms where no such96hardware exists.97 98Note that the DMA API works with any bus independent of the underlying99microprocessor architecture. You should use the DMA API rather than the100bus-specific DMA API, i.e., use the dma_map_*() interfaces rather than the101pci_map_*() interfaces.102 103First of all, you should make sure::104 105 #include <linux/dma-mapping.h>106 107is in your driver, which provides the definition of dma_addr_t. This type108can hold any valid DMA address for the platform and should be used109everywhere you hold a DMA address returned from the DMA mapping functions.110 111What memory is DMA'able?112========================113 114The first piece of information you must know is what kernel memory can115be used with the DMA mapping facilities. There has been an unwritten116set of rules regarding this, and this text is an attempt to finally117write them down.118 119If you acquired your memory via the page allocator120(i.e. __get_free_page*()) or the generic memory allocators121(i.e. kmalloc() or kmem_cache_alloc()) then you may DMA to/from122that memory using the addresses returned from those routines.123 124This means specifically that you may _not_ use the memory/addresses125returned from vmalloc() for DMA. It is possible to DMA to the126_underlying_ memory mapped into a vmalloc() area, but this requires127walking page tables to get the physical addresses, and then128translating each of those pages back to a kernel address using129something like __va(). [ EDIT: Update this when we integrate130Gerd Knorr's generic code which does this. ]131 132This rule also means that you may use neither kernel image addresses133(items in data/text/bss segments), nor module image addresses, nor134stack addresses for DMA. These could all be mapped somewhere entirely135different than the rest of physical memory. Even if those classes of136memory could physically work with DMA, you'd need to ensure the I/O137buffers were cacheline-aligned. Without that, you'd see cacheline138sharing problems (data corruption) on CPUs with DMA-incoherent caches.139(The CPU could write to one word, DMA would write to a different one140in the same cache line, and one of them could be overwritten.)141 142Also, this means that you cannot take the return of a kmap()143call and DMA to/from that. This is similar to vmalloc().144 145What about block I/O and networking buffers? The block I/O and146networking subsystems make sure that the buffers they use are valid147for you to DMA from/to.148 149DMA addressing capabilities150===========================151 152By default, the kernel assumes that your device can address 32-bits of DMA153addressing. For a 64-bit capable device, this needs to be increased, and for154a device with limitations, it needs to be decreased.155 156Special note about PCI: PCI-X specification requires PCI-X devices to support15764-bit addressing (DAC) for all transactions. And at least one platform (SGI158SN2) requires 64-bit consistent allocations to operate correctly when the IO159bus is in PCI-X mode.160 161For correct operation, you must set the DMA mask to inform the kernel about162your devices DMA addressing capabilities.163 164This is performed via a call to dma_set_mask_and_coherent()::165 166 int dma_set_mask_and_coherent(struct device *dev, u64 mask);167 168which will set the mask for both streaming and coherent APIs together. If you169have some special requirements, then the following two separate calls can be170used instead:171 172 The setup for streaming mappings is performed via a call to173 dma_set_mask()::174 175 int dma_set_mask(struct device *dev, u64 mask);176 177 The setup for consistent allocations is performed via a call178 to dma_set_coherent_mask()::179 180 int dma_set_coherent_mask(struct device *dev, u64 mask);181 182Here, dev is a pointer to the device struct of your device, and mask is a bit183mask describing which bits of an address your device supports. Often the184device struct of your device is embedded in the bus-specific device struct of185your device. For example, &pdev->dev is a pointer to the device struct of a186PCI device (pdev is a pointer to the PCI device struct of your device).187 188These calls usually return zero to indicate your device can perform DMA189properly on the machine given the address mask you provided, but they might190return an error if the mask is too small to be supportable on the given191system. If it returns non-zero, your device cannot perform DMA properly on192this platform, and attempting to do so will result in undefined behavior.193You must not use DMA on this device unless the dma_set_mask family of194functions has returned success.195 196This means that in the failure case, you have two options:197 1981) Use some non-DMA mode for data transfer, if possible.1992) Ignore this device and do not initialize it.200 201It is recommended that your driver print a kernel KERN_WARNING message when202setting the DMA mask fails. In this manner, if a user of your driver reports203that performance is bad or that the device is not even detected, you can ask204them for the kernel messages to find out exactly why.205 206The 24-bit addressing device would do something like this::207 208 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(24))) {209 dev_warn(dev, "mydev: No suitable DMA available\n");210 goto ignore_this_device;211 }212 213The standard 64-bit addressing device would do something like this::214 215 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))216 217dma_set_mask_and_coherent() never return fail when DMA_BIT_MASK(64). Typical218error code like::219 220 /* Wrong code */221 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)))222 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))223 224dma_set_mask_and_coherent() will never return failure when bigger than 32.225So typical code like::226 227 /* Recommended code */228 if (support_64bit)229 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));230 else231 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));232 233If the device only supports 32-bit addressing for descriptors in the234coherent allocations, but supports full 64-bits for streaming mappings235it would look like this::236 237 if (dma_set_mask(dev, DMA_BIT_MASK(64))) {238 dev_warn(dev, "mydev: No suitable DMA available\n");239 goto ignore_this_device;240 }241 242The coherent mask will always be able to set the same or a smaller mask as243the streaming mask. However for the rare case that a device driver only244uses consistent allocations, one would have to check the return value from245dma_set_coherent_mask().246 247Finally, if your device can only drive the low 24-bits of248address you might do something like::249 250 if (dma_set_mask(dev, DMA_BIT_MASK(24))) {251 dev_warn(dev, "mydev: 24-bit DMA addressing not available\n");252 goto ignore_this_device;253 }254 255When dma_set_mask() or dma_set_mask_and_coherent() is successful, and256returns zero, the kernel saves away this mask you have provided. The257kernel will use this information later when you make DMA mappings.258 259There is a case which we are aware of at this time, which is worth260mentioning in this documentation. If your device supports multiple261functions (for example a sound card provides playback and record262functions) and the various different functions have _different_263DMA addressing limitations, you may wish to probe each mask and264only provide the functionality which the machine can handle. It265is important that the last call to dma_set_mask() be for the266most specific mask.267 268Here is pseudo-code showing how this might be done::269 270 #define PLAYBACK_ADDRESS_BITS DMA_BIT_MASK(32)271 #define RECORD_ADDRESS_BITS DMA_BIT_MASK(24)272 273 struct my_sound_card *card;274 struct device *dev;275 276 ...277 if (!dma_set_mask(dev, PLAYBACK_ADDRESS_BITS)) {278 card->playback_enabled = 1;279 } else {280 card->playback_enabled = 0;281 dev_warn(dev, "%s: Playback disabled due to DMA limitations\n",282 card->name);283 }284 if (!dma_set_mask(dev, RECORD_ADDRESS_BITS)) {285 card->record_enabled = 1;286 } else {287 card->record_enabled = 0;288 dev_warn(dev, "%s: Record disabled due to DMA limitations\n",289 card->name);290 }291 292A sound card was used as an example here because this genre of PCI293devices seems to be littered with ISA chips given a PCI front end,294and thus retaining the 16MB DMA addressing limitations of ISA.295 296Types of DMA mappings297=====================298 299There are two types of DMA mappings:300 301- Consistent DMA mappings which are usually mapped at driver302 initialization, unmapped at the end and for which the hardware should303 guarantee that the device and the CPU can access the data304 in parallel and will see updates made by each other without any305 explicit software flushing.306 307 Think of "consistent" as "synchronous" or "coherent".308 309 The current default is to return consistent memory in the low 32310 bits of the DMA space. However, for future compatibility you should311 set the consistent mask even if this default is fine for your312 driver.313 314 Good examples of what to use consistent mappings for are:315 316 - Network card DMA ring descriptors.317 - SCSI adapter mailbox command data structures.318 - Device firmware microcode executed out of319 main memory.320 321 The invariant these examples all require is that any CPU store322 to memory is immediately visible to the device, and vice323 versa. Consistent mappings guarantee this.324 325 .. important::326 327 Consistent DMA memory does not preclude the usage of328 proper memory barriers. The CPU may reorder stores to329 consistent memory just as it may normal memory. Example:330 if it is important for the device to see the first word331 of a descriptor updated before the second, you must do332 something like::333 334 desc->word0 = address;335 wmb();336 desc->word1 = DESC_VALID;337 338 in order to get correct behavior on all platforms.339 340 Also, on some platforms your driver may need to flush CPU write341 buffers in much the same way as it needs to flush write buffers342 found in PCI bridges (such as by reading a register's value343 after writing it).344 345- Streaming DMA mappings which are usually mapped for one DMA346 transfer, unmapped right after it (unless you use dma_sync_* below)347 and for which hardware can optimize for sequential accesses.348 349 Think of "streaming" as "asynchronous" or "outside the coherency350 domain".351 352 Good examples of what to use streaming mappings for are:353 354 - Networking buffers transmitted/received by a device.355 - Filesystem buffers written/read by a SCSI device.356 357 The interfaces for using this type of mapping were designed in358 such a way that an implementation can make whatever performance359 optimizations the hardware allows. To this end, when using360 such mappings you must be explicit about what you want to happen.361 362Neither type of DMA mapping has alignment restrictions that come from363the underlying bus, although some devices may have such restrictions.364Also, systems with caches that aren't DMA-coherent will work better365when the underlying buffers don't share cache lines with other data.366 367 368Using Consistent DMA mappings369=============================370 371To allocate and map large (PAGE_SIZE or so) consistent DMA regions,372you should do::373 374 dma_addr_t dma_handle;375 376 cpu_addr = dma_alloc_coherent(dev, size, &dma_handle, gfp);377 378where device is a ``struct device *``. This may be called in interrupt379context with the GFP_ATOMIC flag.380 381Size is the length of the region you want to allocate, in bytes.382 383This routine will allocate RAM for that region, so it acts similarly to384__get_free_pages() (but takes size instead of a page order). If your385driver needs regions sized smaller than a page, you may prefer using386the dma_pool interface, described below.387 388The consistent DMA mapping interfaces, will by default return a DMA address389which is 32-bit addressable. Even if the device indicates (via the DMA mask)390that it may address the upper 32-bits, consistent allocation will only391return > 32-bit addresses for DMA if the consistent DMA mask has been392explicitly changed via dma_set_coherent_mask(). This is true of the393dma_pool interface as well.394 395dma_alloc_coherent() returns two values: the virtual address which you396can use to access it from the CPU and dma_handle which you pass to the397card.398 399The CPU virtual address and the DMA address are both400guaranteed to be aligned to the smallest PAGE_SIZE order which401is greater than or equal to the requested size. This invariant402exists (for example) to guarantee that if you allocate a chunk403which is smaller than or equal to 64 kilobytes, the extent of the404buffer you receive will not cross a 64K boundary.405 406To unmap and free such a DMA region, you call::407 408 dma_free_coherent(dev, size, cpu_addr, dma_handle);409 410where dev, size are the same as in the above call and cpu_addr and411dma_handle are the values dma_alloc_coherent() returned to you.412This function may not be called in interrupt context.413 414If your driver needs lots of smaller memory regions, you can write415custom code to subdivide pages returned by dma_alloc_coherent(),416or you can use the dma_pool API to do that. A dma_pool is like417a kmem_cache, but it uses dma_alloc_coherent(), not __get_free_pages().418Also, it understands common hardware constraints for alignment,419like queue heads needing to be aligned on N byte boundaries.420 421Create a dma_pool like this::422 423 struct dma_pool *pool;424 425 pool = dma_pool_create(name, dev, size, align, boundary);426 427The "name" is for diagnostics (like a kmem_cache name); dev and size428are as above. The device's hardware alignment requirement for this429type of data is "align" (which is expressed in bytes, and must be a430power of two). If your device has no boundary crossing restrictions,431pass 0 for boundary; passing 4096 says memory allocated from this pool432must not cross 4KByte boundaries (but at that time it may be better to433use dma_alloc_coherent() directly instead).434 435Allocate memory from a DMA pool like this::436 437 cpu_addr = dma_pool_alloc(pool, flags, &dma_handle);438 439flags are GFP_KERNEL if blocking is permitted (not in_interrupt nor440holding SMP locks), GFP_ATOMIC otherwise. Like dma_alloc_coherent(),441this returns two values, cpu_addr and dma_handle.442 443Free memory that was allocated from a dma_pool like this::444 445 dma_pool_free(pool, cpu_addr, dma_handle);446 447where pool is what you passed to dma_pool_alloc(), and cpu_addr and448dma_handle are the values dma_pool_alloc() returned. This function449may be called in interrupt context.450 451Destroy a dma_pool by calling::452 453 dma_pool_destroy(pool);454 455Make sure you've called dma_pool_free() for all memory allocated456from a pool before you destroy the pool. This function may not457be called in interrupt context.458 459DMA Direction460=============461 462The interfaces described in subsequent portions of this document463take a DMA direction argument, which is an integer and takes on464one of the following values::465 466 DMA_BIDIRECTIONAL467 DMA_TO_DEVICE468 DMA_FROM_DEVICE469 DMA_NONE470 471You should provide the exact DMA direction if you know it.472 473DMA_TO_DEVICE means "from main memory to the device"474DMA_FROM_DEVICE means "from the device to main memory"475It is the direction in which the data moves during the DMA476transfer.477 478You are _strongly_ encouraged to specify this as precisely479as you possibly can.480 481If you absolutely cannot know the direction of the DMA transfer,482specify DMA_BIDIRECTIONAL. It means that the DMA can go in483either direction. The platform guarantees that you may legally484specify this, and that it will work, but this may be at the485cost of performance for example.486 487The value DMA_NONE is to be used for debugging. One can488hold this in a data structure before you come to know the489precise direction, and this will help catch cases where your490direction tracking logic has failed to set things up properly.491 492Another advantage of specifying this value precisely (outside of493potential platform-specific optimizations of such) is for debugging.494Some platforms actually have a write permission boolean which DMA495mappings can be marked with, much like page protections in the user496program address space. Such platforms can and do report errors in the497kernel logs when the DMA controller hardware detects violation of the498permission setting.499 500Only streaming mappings specify a direction, consistent mappings501implicitly have a direction attribute setting of502DMA_BIDIRECTIONAL.503 504The SCSI subsystem tells you the direction to use in the505'sc_data_direction' member of the SCSI command your driver is506working on.507 508For Networking drivers, it's a rather simple affair. For transmit509packets, map/unmap them with the DMA_TO_DEVICE direction510specifier. For receive packets, just the opposite, map/unmap them511with the DMA_FROM_DEVICE direction specifier.512 513Using Streaming DMA mappings514============================515 516The streaming DMA mapping routines can be called from interrupt517context. There are two versions of each map/unmap, one which will518map/unmap a single memory region, and one which will map/unmap a519scatterlist.520 521To map a single region, you do::522 523 struct device *dev = &my_dev->dev;524 dma_addr_t dma_handle;525 void *addr = buffer->ptr;526 size_t size = buffer->len;527 528 dma_handle = dma_map_single(dev, addr, size, direction);529 if (dma_mapping_error(dev, dma_handle)) {530 /*531 * reduce current DMA mapping usage,532 * delay and try again later or533 * reset driver.534 */535 goto map_error_handling;536 }537 538and to unmap it::539 540 dma_unmap_single(dev, dma_handle, size, direction);541 542You should call dma_mapping_error() as dma_map_single() could fail and return543error. Doing so will ensure that the mapping code will work correctly on all544DMA implementations without any dependency on the specifics of the underlying545implementation. Using the returned address without checking for errors could546result in failures ranging from panics to silent data corruption. The same547applies to dma_map_page() as well.548 549You should call dma_unmap_single() when the DMA activity is finished, e.g.,550from the interrupt which told you that the DMA transfer is done.551 552Using CPU pointers like this for single mappings has a disadvantage:553you cannot reference HIGHMEM memory in this way. Thus, there is a554map/unmap interface pair akin to dma_{map,unmap}_single(). These555interfaces deal with page/offset pairs instead of CPU pointers.556Specifically::557 558 struct device *dev = &my_dev->dev;559 dma_addr_t dma_handle;560 struct page *page = buffer->page;561 unsigned long offset = buffer->offset;562 size_t size = buffer->len;563 564 dma_handle = dma_map_page(dev, page, offset, size, direction);565 if (dma_mapping_error(dev, dma_handle)) {566 /*567 * reduce current DMA mapping usage,568 * delay and try again later or569 * reset driver.570 */571 goto map_error_handling;572 }573 574 ...575 576 dma_unmap_page(dev, dma_handle, size, direction);577 578Here, "offset" means byte offset within the given page.579 580You should call dma_mapping_error() as dma_map_page() could fail and return581error as outlined under the dma_map_single() discussion.582 583You should call dma_unmap_page() when the DMA activity is finished, e.g.,584from the interrupt which told you that the DMA transfer is done.585 586With scatterlists, you map a region gathered from several regions by::587 588 int i, count = dma_map_sg(dev, sglist, nents, direction);589 struct scatterlist *sg;590 591 for_each_sg(sglist, sg, count, i) {592 hw_address[i] = sg_dma_address(sg);593 hw_len[i] = sg_dma_len(sg);594 }595 596where nents is the number of entries in the sglist.597 598The implementation is free to merge several consecutive sglist entries599into one (e.g. if DMA mapping is done with PAGE_SIZE granularity, any600consecutive sglist entries can be merged into one provided the first one601ends and the second one starts on a page boundary - in fact this is a huge602advantage for cards which either cannot do scatter-gather or have very603limited number of scatter-gather entries) and returns the actual number604of sg entries it mapped them to. On failure 0 is returned.605 606Then you should loop count times (note: this can be less than nents times)607and use sg_dma_address() and sg_dma_len() macros where you previously608accessed sg->address and sg->length as shown above.609 610To unmap a scatterlist, just call::611 612 dma_unmap_sg(dev, sglist, nents, direction);613 614Again, make sure DMA activity has already finished.615 616.. note::617 618 The 'nents' argument to the dma_unmap_sg call must be619 the _same_ one you passed into the dma_map_sg call,620 it should _NOT_ be the 'count' value _returned_ from the621 dma_map_sg call.622 623Every dma_map_{single,sg}() call should have its dma_unmap_{single,sg}()624counterpart, because the DMA address space is a shared resource and625you could render the machine unusable by consuming all DMA addresses.626 627If you need to use the same streaming DMA region multiple times and touch628the data in between the DMA transfers, the buffer needs to be synced629properly in order for the CPU and device to see the most up-to-date and630correct copy of the DMA buffer.631 632So, firstly, just map it with dma_map_{single,sg}(), and after each DMA633transfer call either::634 635 dma_sync_single_for_cpu(dev, dma_handle, size, direction);636 637or::638 639 dma_sync_sg_for_cpu(dev, sglist, nents, direction);640 641as appropriate.642 643Then, if you wish to let the device get at the DMA area again,644finish accessing the data with the CPU, and then before actually645giving the buffer to the hardware call either::646 647 dma_sync_single_for_device(dev, dma_handle, size, direction);648 649or::650 651 dma_sync_sg_for_device(dev, sglist, nents, direction);652 653as appropriate.654 655.. note::656 657 The 'nents' argument to dma_sync_sg_for_cpu() and658 dma_sync_sg_for_device() must be the same passed to659 dma_map_sg(). It is _NOT_ the count returned by660 dma_map_sg().661 662After the last DMA transfer call one of the DMA unmap routines663dma_unmap_{single,sg}(). If you don't touch the data from the first664dma_map_*() call till dma_unmap_*(), then you don't have to call the665dma_sync_*() routines at all.666 667Here is pseudo code which shows a situation in which you would need668to use the dma_sync_*() interfaces::669 670 my_card_setup_receive_buffer(struct my_card *cp, char *buffer, int len)671 {672 dma_addr_t mapping;673 674 mapping = dma_map_single(cp->dev, buffer, len, DMA_FROM_DEVICE);675 if (dma_mapping_error(cp->dev, mapping)) {676 /*677 * reduce current DMA mapping usage,678 * delay and try again later or679 * reset driver.680 */681 goto map_error_handling;682 }683 684 cp->rx_buf = buffer;685 cp->rx_len = len;686 cp->rx_dma = mapping;687 688 give_rx_buf_to_card(cp);689 }690 691 ...692 693 my_card_interrupt_handler(int irq, void *devid, struct pt_regs *regs)694 {695 struct my_card *cp = devid;696 697 ...698 if (read_card_status(cp) == RX_BUF_TRANSFERRED) {699 struct my_card_header *hp;700 701 /* Examine the header to see if we wish702 * to accept the data. But synchronize703 * the DMA transfer with the CPU first704 * so that we see updated contents.705 */706 dma_sync_single_for_cpu(&cp->dev, cp->rx_dma,707 cp->rx_len,708 DMA_FROM_DEVICE);709 710 /* Now it is safe to examine the buffer. */711 hp = (struct my_card_header *) cp->rx_buf;712 if (header_is_ok(hp)) {713 dma_unmap_single(&cp->dev, cp->rx_dma, cp->rx_len,714 DMA_FROM_DEVICE);715 pass_to_upper_layers(cp->rx_buf);716 make_and_setup_new_rx_buf(cp);717 } else {718 /* CPU should not write to719 * DMA_FROM_DEVICE-mapped area,720 * so dma_sync_single_for_device() is721 * not needed here. It would be required722 * for DMA_BIDIRECTIONAL mapping if723 * the memory was modified.724 */725 give_rx_buf_to_card(cp);726 }727 }728 }729 730Handling Errors731===============732 733DMA address space is limited on some architectures and an allocation734failure can be determined by:735 736- checking if dma_alloc_coherent() returns NULL or dma_map_sg returns 0737 738- checking the dma_addr_t returned from dma_map_single() and dma_map_page()739 by using dma_mapping_error()::740 741 dma_addr_t dma_handle;742 743 dma_handle = dma_map_single(dev, addr, size, direction);744 if (dma_mapping_error(dev, dma_handle)) {745 /*746 * reduce current DMA mapping usage,747 * delay and try again later or748 * reset driver.749 */750 goto map_error_handling;751 }752 753- unmap pages that are already mapped, when mapping error occurs in the middle754 of a multiple page mapping attempt. These example are applicable to755 dma_map_page() as well.756 757Example 1::758 759 dma_addr_t dma_handle1;760 dma_addr_t dma_handle2;761 762 dma_handle1 = dma_map_single(dev, addr, size, direction);763 if (dma_mapping_error(dev, dma_handle1)) {764 /*765 * reduce current DMA mapping usage,766 * delay and try again later or767 * reset driver.768 */769 goto map_error_handling1;770 }771 dma_handle2 = dma_map_single(dev, addr, size, direction);772 if (dma_mapping_error(dev, dma_handle2)) {773 /*774 * reduce current DMA mapping usage,775 * delay and try again later or776 * reset driver.777 */778 goto map_error_handling2;779 }780 781 ...782 783 map_error_handling2:784 dma_unmap_single(dma_handle1);785 map_error_handling1:786 787Example 2::788 789 /*790 * if buffers are allocated in a loop, unmap all mapped buffers when791 * mapping error is detected in the middle792 */793 794 dma_addr_t dma_addr;795 dma_addr_t array[DMA_BUFFERS];796 int save_index = 0;797 798 for (i = 0; i < DMA_BUFFERS; i++) {799 800 ...801 802 dma_addr = dma_map_single(dev, addr, size, direction);803 if (dma_mapping_error(dev, dma_addr)) {804 /*805 * reduce current DMA mapping usage,806 * delay and try again later or807 * reset driver.808 */809 goto map_error_handling;810 }811 array[i].dma_addr = dma_addr;812 save_index++;813 }814 815 ...816 817 map_error_handling:818 819 for (i = 0; i < save_index; i++) {820 821 ...822 823 dma_unmap_single(array[i].dma_addr);824 }825 826Networking drivers must call dev_kfree_skb() to free the socket buffer827and return NETDEV_TX_OK if the DMA mapping fails on the transmit hook828(ndo_start_xmit). This means that the socket buffer is just dropped in829the failure case.830 831SCSI drivers must return SCSI_MLQUEUE_HOST_BUSY if the DMA mapping832fails in the queuecommand hook. This means that the SCSI subsystem833passes the command to the driver again later.834 835Optimizing Unmap State Space Consumption836========================================837 838On many platforms, dma_unmap_{single,page}() is simply a nop.839Therefore, keeping track of the mapping address and length is a waste840of space. Instead of filling your drivers up with ifdefs and the like841to "work around" this (which would defeat the whole purpose of a842portable API) the following facilities are provided.843 844Actually, instead of describing the macros one by one, we'll845transform some example code.846 8471) Use DEFINE_DMA_UNMAP_{ADDR,LEN} in state saving structures.848 Example, before::849 850 struct ring_state {851 struct sk_buff *skb;852 dma_addr_t mapping;853 __u32 len;854 };855 856 after::857 858 struct ring_state {859 struct sk_buff *skb;860 DEFINE_DMA_UNMAP_ADDR(mapping);861 DEFINE_DMA_UNMAP_LEN(len);862 };863 8642) Use dma_unmap_{addr,len}_set() to set these values.865 Example, before::866 867 ringp->mapping = FOO;868 ringp->len = BAR;869 870 after::871 872 dma_unmap_addr_set(ringp, mapping, FOO);873 dma_unmap_len_set(ringp, len, BAR);874 8753) Use dma_unmap_{addr,len}() to access these values.876 Example, before::877 878 dma_unmap_single(dev, ringp->mapping, ringp->len,879 DMA_FROM_DEVICE);880 881 after::882 883 dma_unmap_single(dev,884 dma_unmap_addr(ringp, mapping),885 dma_unmap_len(ringp, len),886 DMA_FROM_DEVICE);887 888It really should be self-explanatory. We treat the ADDR and LEN889separately, because it is possible for an implementation to only890need the address in order to perform the unmap operation.891 892Platform Issues893===============894 895If you are just writing drivers for Linux and do not maintain896an architecture port for the kernel, you can safely skip down897to "Closing".898 8991) Struct scatterlist requirements.900 901 You need to enable CONFIG_NEED_SG_DMA_LENGTH if the architecture902 supports IOMMUs (including software IOMMU).903 9042) ARCH_DMA_MINALIGN905 906 Architectures must ensure that kmalloc'ed buffer is907 DMA-safe. Drivers and subsystems depend on it. If an architecture908 isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in909 the CPU cache is identical to data in main memory),910 ARCH_DMA_MINALIGN must be set so that the memory allocator911 makes sure that kmalloc'ed buffer doesn't share a cache line with912 the others. See arch/arm/include/asm/cache.h as an example.913 914 Note that ARCH_DMA_MINALIGN is about DMA memory alignment915 constraints. You don't need to worry about the architecture data916 alignment constraints (e.g. the alignment constraints about 64-bit917 objects).918 919Closing920=======921 922This document, and the API itself, would not be in its current923form without the feedback and suggestions from numerous individuals.924We would like to specifically mention, in no particular order, the925following people::926 927 Russell King <rmk@arm.linux.org.uk>928 Leo Dagum <dagum@barrel.engr.sgi.com>929 Ralf Baechle <ralf@oss.sgi.com>930 Grant Grundler <grundler@cup.hp.com>931 Jay Estabrook <Jay.Estabrook@compaq.com>932 Thomas Sailer <sailer@ife.ee.ethz.ch>933 Andrea Arcangeli <andrea@suse.de>934 Jens Axboe <jens.axboe@oracle.com>935 David Mosberger-Tang <davidm@hpl.hp.com>936