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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Arm Coresight Address Translation Unit (CATU)8 9maintainers:10 - Mathieu Poirier <mathieu.poirier@linaro.org>11 - Mike Leach <mike.leach@linaro.org>12 - Leo Yan <leo.yan@linaro.org>13 - Suzuki K Poulose <suzuki.poulose@arm.com>14 15description: |16 CoreSight components are compliant with the ARM CoreSight architecture17 specification and can be connected in various topologies to suit a particular18 SoCs tracing needs. These trace components can generally be classified as19 sinks, links and sources. Trace data produced by one or more sources flows20 through the intermediate links connecting the source to the currently selected21 sink.22 23 The CoreSight Address Translation Unit (CATU) translates addresses between an24 AXI master and system memory. The CATU is normally used along with the TMC to25 implement scattering of virtual trace buffers in physical memory. The CATU26 translates contiguous Virtual Addresses (VAs) from an AXI master into27 non-contiguous Physical Addresses (PAs) that are intended for system memory.28 29# Need a custom select here or 'arm,primecell' will match on lots of nodes30select:31 properties:32 compatible:33 contains:34 const: arm,coresight-catu35 required:36 - compatible37 38allOf:39 - $ref: /schemas/arm/primecell.yaml#40 41properties:42 compatible:43 items:44 - const: arm,coresight-catu45 - const: arm,primecell46 47 reg:48 maxItems: 149 50 clocks:51 minItems: 152 maxItems: 253 54 clock-names:55 minItems: 156 items:57 - const: apb_pclk58 - const: atclk59 60 interrupts:61 maxItems: 162 description: Address translation error interrupt63 64 power-domains:65 maxItems: 166 67 in-ports:68 $ref: /schemas/graph.yaml#/properties/ports69 additionalProperties: false70 71 properties:72 port:73 description: AXI Slave connected to another Coresight component74 $ref: /schemas/graph.yaml#/properties/port75 76required:77 - compatible78 - reg79 - clocks80 - clock-names81 - in-ports82 83unevaluatedProperties: false84 85examples:86 - |87 #include <dt-bindings/interrupt-controller/arm-gic.h>88 catu@207e0000 {89 compatible = "arm,coresight-catu", "arm,primecell";90 reg = <0x207e0000 0x1000>;91 92 clocks = <&oscclk6a>;93 clock-names = "apb_pclk";94 95 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;96 in-ports {97 port {98 catu_in_port: endpoint {99 remote-endpoint = <&etr_out_port>;100 };101 };102 };103 };104...105