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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2# Copyright 2019 Linaro Ltd.3%YAML 1.24---5$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: ARM Coresight Cross Trigger Interface (CTI) device.9 10description: |11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.14 The ECT components are not part of the trace generation data path and are thus15 not part of the CoreSight graph.16 17 The CTI component properties define the connections between the individual18 CTI and the components it is directly connected to, consisting of input and19 output hardware trigger signals. CTIs can have a maximum number of input and20 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The21 number is defined at design time, the maximum of each defined in the DEVID22 register.23 24 CTIs are interconnected in a star topology via the CTM, using a number of25 programmable channels, usually 4, but again implementation defined and26 described in the DEVID register. The star topology is not required to be27 described in the bindings as the actual connections are software28 programmable.29 30 In general the connections between CTI and components via the trigger signals31 are implementation defined, except when the CTI is connected to an ARM v832 architecture core and optional ETM.33 34 In this case the ARM v8 architecture defines the required signal connections35 between CTI and the CPU core and ETM if present. In the case of a v836 architecturally connected CTI an additional compatible string is used to37 indicate this feature (arm,coresight-cti-v8-arch).38 39 When CTI trigger connection information is unavailable then a minimal driver40 binding can be declared with no explicit trigger signals. This will result41 the driver detecting the maximum available triggers and channels from the42 DEVID register and make them all available for use as a single default43 connection. Any user / client application will require additional information44 on the connections between the CTI and other components for correct operation.45 This information might be found by enabling the Integration Test registers in46 the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel47 configuration). These registers may be used to explore the trigger connections48 between CTI and other CoreSight components.49 50 Certain triggers between CoreSight devices and the CTI have specific types51 and usages. These can be defined along with the signal indexes with the52 constants defined in <dt-bindings/arm/coresight-cti-dt.h>53 54 For example a CTI connected to a core will usually have a DBGREQ signal. This55 is defined in the binding as type PE_EDBGREQ. These types will appear in an56 optional array alongside the signal indexes. Omitting types will default all57 signals to GEN_IO.58 59 Note that some hardware trigger signals can be connected to non-CoreSight60 components (e.g. UART etc) depending on hardware implementation.61 62maintainers:63 - Mike Leach <mike.leach@linaro.org>64 65allOf:66 - $ref: /schemas/arm/primecell.yaml#67 68# Need a custom select here or 'arm,primecell' will match on lots of nodes69select:70 properties:71 compatible:72 contains:73 enum:74 - arm,coresight-cti75 required:76 - compatible77 78properties:79 $nodename:80 pattern: "^cti(@[0-9a-f]+)$"81 compatible:82 oneOf:83 - items:84 - const: arm,coresight-cti85 - const: arm,primecell86 - items:87 - const: arm,coresight-cti-v8-arch88 - const: arm,coresight-cti89 - const: arm,primecell90 91 reg:92 maxItems: 193 94 cpu:95 description:96 Handle to cpu this CTI is associated with.97 98 power-domains:99 maxItems: 1100 101 arm,cti-ctm-id:102 $ref: /schemas/types.yaml#/definitions/uint32103 description:104 Defines the CTM this CTI is connected to, in large systems with multiple105 separate CTI/CTM nets. Typically multi-socket systems where the CTM is106 propagated between sockets.107 108 arm,cs-dev-assoc:109 $ref: /schemas/types.yaml#/definitions/phandle110 description:111 defines a phandle reference to an associated CoreSight trace device.112 When the associated trace device is enabled, then the respective CTI113 will be enabled. Use in CTI base node when compatible string114 arm,coresight-cti-v8-arch used. If the associated device has not been115 registered then the node name will be stored as the connection name for116 later resolution. If the associated device is not a CoreSight device or117 not registered then the node name will remain the connection name and118 automatic enabling will not occur.119 120 # size cells and address cells required if trig-conns node present.121 "#size-cells":122 const: 0123 124 "#address-cells":125 const: 1126 127patternProperties:128 '^trig-conns@([0-9]+)$':129 type: object130 additionalProperties: false131 132 description:133 A trigger connections child node which describes the trigger signals134 between this CTI and another hardware device. This device may be a CPU,135 CoreSight device, any other hardware device or simple external IO lines.136 The connection may have both input and output triggers, or only one or the137 other.138 139 properties:140 reg:141 maxItems: 1142 143 cpu:144 description:145 Handle to cpu this trigger connection is associated with.146 147 arm,cs-dev-assoc:148 $ref: /schemas/types.yaml#/definitions/phandle149 description:150 defines a phandle reference to an associated CoreSight trace device.151 When the associated trace device is enabled, then the respective CTI152 will be enabled. If the associated device has not been registered153 then the node name will be stored as the connection name for later154 resolution. If the associated device is not a CoreSight device or155 not registered then the node name will remain the connection name156 and automatic enabling will not occur.157 158 arm,trig-in-sigs:159 $ref: /schemas/types.yaml#/definitions/uint32-array160 minItems: 1161 maxItems: 32162 description:163 List of CTI trigger in signal numbers in use by a trig-conns node.164 165 arm,trig-in-types:166 $ref: /schemas/types.yaml#/definitions/uint32-array167 minItems: 1168 maxItems: 32169 description:170 List of constants representing the types for the CTI trigger in171 signals. Types in this array match to the corresponding signal in the172 arm,trig-in-sigs array. If the -types array is smaller, or omitted173 completely, then the types will default to GEN_IO.174 175 arm,trig-out-sigs:176 $ref: /schemas/types.yaml#/definitions/uint32-array177 minItems: 1178 maxItems: 32179 description:180 List of CTI trigger out signal numbers in use by a trig-conns node.181 182 arm,trig-out-types:183 $ref: /schemas/types.yaml#/definitions/uint32-array184 minItems: 1185 maxItems: 32186 description:187 List of constants representing the types for the CTI trigger out188 signals. Types in this array match to the corresponding signal189 in the arm,trig-out-sigs array. If the "-types" array is smaller,190 or omitted completely, then the types will default to GEN_IO.191 192 arm,trig-filters:193 $ref: /schemas/types.yaml#/definitions/uint32-array194 minItems: 1195 maxItems: 32196 description:197 List of CTI trigger out signals that will be blocked from becoming198 active, unless filtering is disabled on the driver.199 200 arm,trig-conn-name:201 $ref: /schemas/types.yaml#/definitions/string202 description:203 Defines a connection name that will be displayed, if the cpu or204 arm,cs-dev-assoc properties are not being used in this connection.205 Principle use for CTI that are connected to non-CoreSight devices, or206 external IO.207 208 anyOf:209 - required:210 - arm,trig-in-sigs211 - required:212 - arm,trig-out-sigs213 oneOf:214 - required:215 - arm,trig-conn-name216 - required:217 - cpu218 - required:219 - arm,cs-dev-assoc220 required:221 - reg222 223required:224 - compatible225 - reg226 - clocks227 - clock-names228 229if:230 properties:231 compatible:232 contains:233 const: arm,coresight-cti-v8-arch234 235then:236 required:237 - cpu238 239unevaluatedProperties: false240 241examples:242 # minimum CTI definition. DEVID register used to set number of triggers.243 - |244 cti@20020000 {245 compatible = "arm,coresight-cti", "arm,primecell";246 reg = <0x20020000 0x1000>;247 248 clocks = <&soc_smc50mhz>;249 clock-names = "apb_pclk";250 };251 # v8 architecturally defined CTI - CPU + ETM connections generated by the252 # driver according to the v8 architecture specification.253 - |254 cti@859000 {255 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",256 "arm,primecell";257 reg = <0x859000 0x1000>;258 259 clocks = <&soc_smc50mhz>;260 clock-names = "apb_pclk";261 262 cpu = <&CPU1>;263 arm,cs-dev-assoc = <&etm1>;264 };265 # Implementation defined CTI - CPU + ETM connections explicitly defined..266 # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h267 # #size-cells and #address-cells are required if trig-conns@ nodes present.268 - |269 #include <dt-bindings/arm/coresight-cti-dt.h>270 271 cti@858000 {272 compatible = "arm,coresight-cti", "arm,primecell";273 reg = <0x858000 0x1000>;274 275 clocks = <&soc_smc50mhz>;276 clock-names = "apb_pclk";277 278 arm,cti-ctm-id = <1>;279 280 #address-cells = <1>;281 #size-cells = <0>;282 283 trig-conns@0 {284 reg = <0>;285 arm,trig-in-sigs = <4 5 6 7>;286 arm,trig-in-types = <ETM_EXTOUT287 ETM_EXTOUT288 ETM_EXTOUT289 ETM_EXTOUT>;290 arm,trig-out-sigs = <4 5 6 7>;291 arm,trig-out-types = <ETM_EXTIN292 ETM_EXTIN293 ETM_EXTIN294 ETM_EXTIN>;295 arm,cs-dev-assoc = <&etm0>;296 };297 298 trig-conns@1 {299 reg = <1>;300 cpu = <&CPU0>;301 arm,trig-in-sigs = <0 1>;302 arm,trig-in-types = <PE_DBGTRIGGER303 PE_PMUIRQ>;304 arm,trig-out-sigs = <0 1 2 >;305 arm,trig-out-types = <PE_EDBGREQ306 PE_DBGRESTART307 PE_CTIIRQ>;308 309 arm,trig-filters = <0>;310 };311 };312 # Implementation defined CTI - non CoreSight component connections.313 - |314 cti@20110000 {315 compatible = "arm,coresight-cti", "arm,primecell";316 reg = <0x20110000 0x1000>;317 318 clocks = <&soc_smc50mhz>;319 clock-names = "apb_pclk";320 321 #address-cells = <1>;322 #size-cells = <0>;323 324 trig-conns@0 {325 reg = <0>;326 arm,trig-in-sigs = <0>;327 arm,trig-in-types = <GEN_INTREQ>;328 arm,trig-out-sigs = <0>;329 arm,trig-out-types = <GEN_HALTREQ>;330 arm,trig-conn-name = "sys_profiler";331 };332 333 trig-conns@1 {334 reg = <1>;335 arm,trig-out-sigs = <2 3>;336 arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;337 arm,trig-conn-name = "watchdog";338 };339 340 trig-conns@2 {341 reg = <2>;342 arm,trig-in-sigs = <1 6>;343 arm,trig-in-types = <GEN_HALTREQ GEN_RESTARTREQ>;344 arm,trig-conn-name = "g_counter";345 };346 };347 348...349