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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Arm CoreSight System Trace MacroCell8 9maintainers:10 - Mathieu Poirier <mathieu.poirier@linaro.org>11 - Mike Leach <mike.leach@linaro.org>12 - Leo Yan <leo.yan@linaro.org>13 - Suzuki K Poulose <suzuki.poulose@arm.com>14 15description: |16 CoreSight components are compliant with the ARM CoreSight architecture17 specification and can be connected in various topologies to suit a particular18 SoCs tracing needs. These trace components can generally be classified as19 sinks, links and sources. Trace data produced by one or more sources flows20 through the intermediate links connecting the source to the currently selected21 sink.22 23 The STM is a trace source that is integrated into a CoreSight system, designed24 primarily for high-bandwidth trace of instrumentation embedded into software.25 This instrumentation is made up of memory-mapped writes to the STM Advanced26 eXtensible Interface (AXI) slave, which carry information about the behavior27 of the software.28 29select:30 properties:31 compatible:32 contains:33 const: arm,coresight-stm34 required:35 - compatible36 37allOf:38 - $ref: /schemas/arm/primecell.yaml#39 40properties:41 compatible:42 items:43 - const: arm,coresight-stm44 - const: arm,primecell45 46 reg:47 maxItems: 248 49 reg-names:50 items:51 - const: stm-base52 - const: stm-stimulus-base53 54 clocks:55 minItems: 156 maxItems: 257 58 clock-names:59 minItems: 160 items:61 - const: apb_pclk62 - const: atclk63 64 power-domains:65 maxItems: 166 67 out-ports:68 $ref: /schemas/graph.yaml#/properties/ports69 additionalProperties: false70 71 properties:72 port:73 description: Output connection to the CoreSight Trace bus.74 $ref: /schemas/graph.yaml#/properties/port75 76required:77 - compatible78 - reg79 - reg-names80 - clocks81 - clock-names82 - out-ports83 84unevaluatedProperties: false85 86examples:87 - |88 stm@20100000 {89 compatible = "arm,coresight-stm", "arm,primecell";90 reg = <0x20100000 0x1000>,91 <0x28000000 0x180000>;92 reg-names = "stm-base", "stm-stimulus-base";93 94 clocks = <&soc_smc50mhz>;95 clock-names = "apb_pclk";96 out-ports {97 port {98 stm_out_port: endpoint {99 remote-endpoint = <&main_funnel_in_port2>;100 };101 };102 };103 };104...105