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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/arm/cpus.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ARM CPUs8 9maintainers:10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>11 12description: |+13 The device tree allows to describe the layout of CPUs in a system through14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")15 defining properties for every cpu.16 17 Bindings for CPU nodes follow the Devicetree Specification, available from:18 19 https://www.devicetree.org/specifications/20 21 with updates for 32-bit and 64-bit ARM systems provided in this document.22 23 ================================24 Convention used in this document25 ================================26 27 This document follows the conventions described in the Devicetree28 Specification, with the addition:29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in31 the reg property contained in bits 7 down to 032 33 =====================================34 cpus and cpu node bindings definition35 =====================================36 37 The ARM architecture, in accordance with the Devicetree Specification,38 requires the cpus and cpu nodes to be present and contain the properties39 described below.40 41properties:42 reg:43 maxItems: 144 description: |45 Usage and definition depend on ARM architecture version and46 configuration:47 48 On uniprocessor ARM architectures previous to v749 this property is required and must be set to 0.50 51 On ARM 11 MPcore based systems this property is52 required and matches the CPUID[11:0] register bits.53 54 Bits [11:0] in the reg cell must be set to55 bits [11:0] in CPU ID register.56 57 All other bits in the reg cell must be set to 0.58 59 On 32-bit ARM v7 or later systems this property is60 required and matches the CPU MPIDR[23:0] register61 bits.62 63 Bits [23:0] in the reg cell must be set to64 bits [23:0] in MPIDR.65 66 All other bits in the reg cell must be set to 0.67 68 On ARM v8 64-bit systems this property is required69 and matches the MPIDR_EL1 register affinity bits.70 71 * If cpus node's #address-cells property is set to 272 73 The first reg cell bits [7:0] must be set to74 bits [39:32] of MPIDR_EL1.75 76 The second reg cell bits [23:0] must be set to77 bits [23:0] of MPIDR_EL1.78 79 * If cpus node's #address-cells property is set to 180 81 The reg cell bits [23:0] must be set to bits [23:0]82 of MPIDR_EL1.83 84 All other bits in the reg cells must be set to 0.85 86 compatible:87 enum:88 - apple,avalanche89 - apple,blizzard90 - apple,icestorm91 - apple,firestorm92 - arm,arm710t93 - arm,arm720t94 - arm,arm740t95 - arm,arm7ej-s96 - arm,arm7tdmi97 - arm,arm7tdmi-s98 - arm,arm9es99 - arm,arm9ej-s100 - arm,arm920t101 - arm,arm922t102 - arm,arm925103 - arm,arm926e-s104 - arm,arm926ej-s105 - arm,arm940t106 - arm,arm946e-s107 - arm,arm966e-s108 - arm,arm968e-s109 - arm,arm9tdmi110 - arm,arm1020e111 - arm,arm1020t112 - arm,arm1022e113 - arm,arm1026ej-s114 - arm,arm1136j-s115 - arm,arm1136jf-s116 - arm,arm1156t2-s117 - arm,arm1156t2f-s118 - arm,arm1176jzf119 - arm,arm1176jz-s120 - arm,arm1176jzf-s121 - arm,arm11mpcore122 - arm,armv8 # Only for s/w models123 - arm,cortex-a5124 - arm,cortex-a7125 - arm,cortex-a8126 - arm,cortex-a9127 - arm,cortex-a12128 - arm,cortex-a15129 - arm,cortex-a17130 - arm,cortex-a32131 - arm,cortex-a34132 - arm,cortex-a35133 - arm,cortex-a53134 - arm,cortex-a55135 - arm,cortex-a57136 - arm,cortex-a65137 - arm,cortex-a72138 - arm,cortex-a73139 - arm,cortex-a75140 - arm,cortex-a76141 - arm,cortex-a77142 - arm,cortex-a78143 - arm,cortex-a78ae144 - arm,cortex-a78c145 - arm,cortex-a510146 - arm,cortex-a520147 - arm,cortex-a710148 - arm,cortex-a715149 - arm,cortex-a720150 - arm,cortex-a725151 - arm,cortex-m0152 - arm,cortex-m0+153 - arm,cortex-m1154 - arm,cortex-m3155 - arm,cortex-m4156 - arm,cortex-r4157 - arm,cortex-r5158 - arm,cortex-r7159 - arm,cortex-r52160 - arm,cortex-x1161 - arm,cortex-x1c162 - arm,cortex-x2163 - arm,cortex-x3164 - arm,cortex-x4165 - arm,cortex-x925166 - arm,neoverse-e1167 - arm,neoverse-n1168 - arm,neoverse-n2169 - arm,neoverse-n3170 - arm,neoverse-v1171 - arm,neoverse-v2172 - arm,neoverse-v3173 - arm,neoverse-v3ae174 - brcm,brahma-b15175 - brcm,brahma-b53176 - brcm,vulcan177 - cavium,thunder178 - cavium,thunder2179 - faraday,fa526180 - intel,sa110181 - intel,sa1100182 - marvell,feroceon183 - marvell,mohawk184 - marvell,pj4a185 - marvell,pj4b186 - marvell,sheeva-v5187 - marvell,sheeva-v7188 - nvidia,tegra132-denver189 - nvidia,tegra186-denver190 - nvidia,tegra194-carmel191 - qcom,krait192 - qcom,kryo193 - qcom,kryo240194 - qcom,kryo250195 - qcom,kryo260196 - qcom,kryo280197 - qcom,kryo360198 - qcom,kryo385199 - qcom,kryo465200 - qcom,kryo468201 - qcom,kryo485202 - qcom,kryo560203 - qcom,kryo570204 - qcom,kryo660205 - qcom,kryo685206 - qcom,kryo780207 - qcom,oryon208 - qcom,scorpion209 210 enable-method:211 $ref: /schemas/types.yaml#/definitions/string212 oneOf:213 # On ARM v8 64-bit this property is required214 - enum:215 - psci216 - spin-table217 # On ARM 32-bit systems this property is optional218 - enum:219 - actions,s500-smp220 - allwinner,sun6i-a31221 - allwinner,sun8i-a23222 - allwinner,sun9i-a80-smp223 - allwinner,sun8i-a83t-smp224 - amlogic,meson8-smp225 - amlogic,meson8b-smp226 - arm,realview-smp227 - aspeed,ast2600-smp228 - brcm,bcm11351-cpu-method229 - brcm,bcm23550230 - brcm,bcm2836-smp231 - brcm,bcm63138232 - brcm,bcm-nsp-smp233 - brcm,brahma-b15234 - marvell,armada-375-smp235 - marvell,armada-380-smp236 - marvell,armada-390-smp237 - marvell,armada-xp-smp238 - marvell,98dx3236-smp239 - marvell,mmp3-smp240 - mediatek,mt6589-smp241 - mediatek,mt81xx-tz-smp242 - qcom,gcc-msm8660243 - qcom,kpss-acc-v1244 - qcom,kpss-acc-v2245 - qcom,msm8226-smp246 - qcom,msm8909-smp247 # Only valid on ARM 32-bit, see above for ARM v8 64-bit248 - qcom,msm8916-smp249 - renesas,apmu250 - renesas,r9a06g032-smp251 - rockchip,rk3036-smp252 - rockchip,rk3066-smp253 - socionext,milbeaut-m10v-smp254 - ste,dbx500-smp255 - ti,am3352256 - ti,am4372257 258 cpu-release-addr:259 oneOf:260 - $ref: /schemas/types.yaml#/definitions/uint32261 - $ref: /schemas/types.yaml#/definitions/uint64262 description:263 The DT specification defines this as 64-bit always, but some 32-bit Arm264 systems have used a 32-bit value which must be supported.265 Required for systems that have an "enable-method"266 property value of "spin-table".267 268 cpu-idle-states:269 $ref: /schemas/types.yaml#/definitions/phandle-array270 items:271 maxItems: 1272 description: |273 List of phandles to idle state nodes supported274 by this cpu (see ./idle-states.yaml).275 276 capacity-dmips-mhz:277 description:278 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in279 DMIPS/MHz, relative to highest capacity-dmips-mhz280 in the system.281 282 cci-control-port: true283 284 dynamic-power-coefficient:285 $ref: /schemas/types.yaml#/definitions/uint32286 description:287 A u32 value that represents the running time dynamic288 power coefficient in units of uW/MHz/V^2. The289 coefficient can either be calculated from power290 measurements or derived by analysis.291 292 The dynamic power consumption of the CPU is293 proportional to the square of the Voltage (V) and294 the clock frequency (f). The coefficient is used to295 calculate the dynamic power as below -296 297 Pdyn = dynamic-power-coefficient * V^2 * f298 299 where voltage is in V, frequency is in MHz.300 301 performance-domains:302 maxItems: 1303 description:304 List of phandles and performance domain specifiers, as defined by305 bindings of the performance domain provider. See also306 dvfs/performance-domain.yaml.307 308 power-domains:309 description:310 List of phandles and PM domain specifiers, as defined by bindings of the311 PM domain provider (see also ../power_domain.txt).312 313 power-domain-names:314 description:315 A list of power domain name strings sorted in the same order as the316 power-domains property.317 318 For PSCI based platforms, the name corresponding to the index of the PSCI319 PM domain provider, must be "psci". For SCMI based platforms, the name320 corresponding to the index of an SCMI performance domain provider, must be321 "perf".322 323 qcom,saw:324 $ref: /schemas/types.yaml#/definitions/phandle325 description: |326 Specifies the SAW* node associated with this CPU.327 328 Required for systems that have an "enable-method" property329 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"330 331 * arm/msm/qcom,saw2.txt332 333 qcom,acc:334 $ref: /schemas/types.yaml#/definitions/phandle335 description: |336 Specifies the ACC* node associated with this CPU.337 338 Required for systems that have an "enable-method" property339 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or340 "qcom,msm8916-smp".341 342 * arm/msm/qcom,kpss-acc.txt343 344 rockchip,pmu:345 $ref: /schemas/types.yaml#/definitions/phandle346 description: |347 Specifies the syscon node controlling the cpu core power domains.348 349 Optional for systems that have an "enable-method"350 property value of "rockchip,rk3066-smp"351 While optional, it is the preferred way to get access to352 the cpu-core power-domains.353 354 secondary-boot-reg:355 $ref: /schemas/types.yaml#/definitions/uint32356 description: |357 Required for systems that have an "enable-method" property value of358 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".359 360 This includes the following SoCs: |361 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550362 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312363 364 The secondary-boot-reg property is a u32 value that specifies the365 physical address of the register used to request the ROM holding pen366 code release a secondary CPU. The value written to the register is367 formed by encoding the target CPU id into the low bits of the368 physical start address it should jump to.369 370if:371 # If the enable-method property contains one of those values372 properties:373 enable-method:374 contains:375 enum:376 - brcm,bcm11351-cpu-method377 - brcm,bcm23550378 - brcm,bcm-nsp-smp379 # and if enable-method is present380 required:381 - enable-method382 383then:384 required:385 - secondary-boot-reg386 387required:388 - device_type389 - reg390 - compatible391 392dependencies:393 rockchip,pmu: [enable-method]394 395additionalProperties: true396 397examples:398 - |399 cpus {400 #size-cells = <0>;401 #address-cells = <1>;402 403 cpu@0 {404 device_type = "cpu";405 compatible = "arm,cortex-a15";406 reg = <0x0>;407 };408 409 cpu@1 {410 device_type = "cpu";411 compatible = "arm,cortex-a15";412 reg = <0x1>;413 };414 415 cpu@100 {416 device_type = "cpu";417 compatible = "arm,cortex-a7";418 reg = <0x100>;419 };420 421 cpu@101 {422 device_type = "cpu";423 compatible = "arm,cortex-a7";424 reg = <0x101>;425 };426 };427 428 - |429 // Example 2 (Cortex-A8 uniprocessor 32-bit system):430 cpus {431 #size-cells = <0>;432 #address-cells = <1>;433 434 cpu@0 {435 device_type = "cpu";436 compatible = "arm,cortex-a8";437 reg = <0x0>;438 };439 };440 441 - |442 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):443 cpus {444 #size-cells = <0>;445 #address-cells = <1>;446 447 cpu@0 {448 device_type = "cpu";449 compatible = "arm,arm926ej-s";450 reg = <0x0>;451 };452 };453 454 - |455 // Example 4 (ARM Cortex-A57 64-bit system):456 cpus {457 #size-cells = <0>;458 #address-cells = <2>;459 460 cpu@0 {461 device_type = "cpu";462 compatible = "arm,cortex-a57";463 reg = <0x0 0x0>;464 enable-method = "spin-table";465 cpu-release-addr = <0 0x20000000>;466 };467 468 cpu@1 {469 device_type = "cpu";470 compatible = "arm,cortex-a57";471 reg = <0x0 0x1>;472 enable-method = "spin-table";473 cpu-release-addr = <0 0x20000000>;474 };475 476 cpu@100 {477 device_type = "cpu";478 compatible = "arm,cortex-a57";479 reg = <0x0 0x100>;480 enable-method = "spin-table";481 cpu-release-addr = <0 0x20000000>;482 };483 484 cpu@101 {485 device_type = "cpu";486 compatible = "arm,cortex-a57";487 reg = <0x0 0x101>;488 enable-method = "spin-table";489 cpu-release-addr = <0 0x20000000>;490 };491 492 cpu@10000 {493 device_type = "cpu";494 compatible = "arm,cortex-a57";495 reg = <0x0 0x10000>;496 enable-method = "spin-table";497 cpu-release-addr = <0 0x20000000>;498 };499 500 cpu@10001 {501 device_type = "cpu";502 compatible = "arm,cortex-a57";503 reg = <0x0 0x10001>;504 enable-method = "spin-table";505 cpu-release-addr = <0 0x20000000>;506 };507 508 cpu@10100 {509 device_type = "cpu";510 compatible = "arm,cortex-a57";511 reg = <0x0 0x10100>;512 enable-method = "spin-table";513 cpu-release-addr = <0 0x20000000>;514 };515 516 cpu@10101 {517 device_type = "cpu";518 compatible = "arm,cortex-a57";519 reg = <0x0 0x10101>;520 enable-method = "spin-table";521 cpu-release-addr = <0 0x20000000>;522 };523 524 cpu@100000000 {525 device_type = "cpu";526 compatible = "arm,cortex-a57";527 reg = <0x1 0x0>;528 enable-method = "spin-table";529 cpu-release-addr = <0 0x20000000>;530 };531 532 cpu@100000001 {533 device_type = "cpu";534 compatible = "arm,cortex-a57";535 reg = <0x1 0x1>;536 enable-method = "spin-table";537 cpu-release-addr = <0 0x20000000>;538 };539 540 cpu@100000100 {541 device_type = "cpu";542 compatible = "arm,cortex-a57";543 reg = <0x1 0x100>;544 enable-method = "spin-table";545 cpu-release-addr = <0 0x20000000>;546 };547 548 cpu@100000101 {549 device_type = "cpu";550 compatible = "arm,cortex-a57";551 reg = <0x1 0x101>;552 enable-method = "spin-table";553 cpu-release-addr = <0 0x20000000>;554 };555 556 cpu@100010000 {557 device_type = "cpu";558 compatible = "arm,cortex-a57";559 reg = <0x1 0x10000>;560 enable-method = "spin-table";561 cpu-release-addr = <0 0x20000000>;562 };563 564 cpu@100010001 {565 device_type = "cpu";566 compatible = "arm,cortex-a57";567 reg = <0x1 0x10001>;568 enable-method = "spin-table";569 cpu-release-addr = <0 0x20000000>;570 };571 572 cpu@100010100 {573 device_type = "cpu";574 compatible = "arm,cortex-a57";575 reg = <0x1 0x10100>;576 enable-method = "spin-table";577 cpu-release-addr = <0 0x20000000>;578 };579 580 cpu@100010101 {581 device_type = "cpu";582 compatible = "arm,cortex-a57";583 reg = <0x1 0x10101>;584 enable-method = "spin-table";585 cpu-release-addr = <0 0x20000000>;586 };587 };588...589