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1Freescale Vybrid Miscellaneous System Control - Interrupt Router2 3The MSCM IP contains multiple sub modules, this binding describes the second4block of registers which control the interrupt router. The interrupt router5allows to configure the recipient of each peripheral interrupt. Furthermore6it controls the directed processor interrupts. The module is available in all7Vybrid SoC's but is only really useful in dual core configurations (VF6xx8which comes with a Cortex-A5/Cortex-M4 combination).9 10Required properties:11- compatible: "fsl,vf610-mscm-ir"12- reg: the register range of the MSCM Interrupt Router13- fsl,cpucfg: The handle to the MSCM CPU configuration node, required14 to get the current CPU ID15- interrupt-controller: Identifies the node as an interrupt controller16- #interrupt-cells: Two cells, interrupt number and cells.17 The hardware interrupt number according to interrupt18 assignment of the interrupt router is required.19 Flags get passed only when using GIC as parent. Flags20 encoding as documented by the GIC bindings.21 22Example:23 mscm_ir: interrupt-controller@40001800 {24 compatible = "fsl,vf610-mscm-ir";25 reg = <0x40001800 0x400>;26 fsl,cpucfg = <&mscm_cpucfg>;27 interrupt-controller;28 #interrupt-cells = <2>;29 interrupt-parent = <&intc>;30 }31