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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Hisilicon system controller8 9maintainers:10 - Wei Xu <xuwei5@hisilicon.com>11 12description: |13 The Hisilicon system controller is used on many Hisilicon boards, it can be14 used to assist the slave core startup, reboot the system, etc.15 16 There are some variants of the Hisilicon system controller, such as HiP01,17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the18 Hisilicon system controller, but some same registers located at different19 offset. In addition, the HiP01 system controller has some specific control20 registers for HIP01 SoC family, such as slave core boot.21 22 The compatible names of each system controller are as follows:23 Hisilicon system controller --> hisilicon,sysctrl24 HiP01 system controller --> hisilicon,hip01-sysctrl25 Hi6220 system controller --> hisilicon,hi6220-sysctrl26 Hi3519 system controller --> hisilicon,hi3519-sysctrl27 28allOf:29 - if:30 properties:31 compatible:32 contains:33 const: hisilicon,hi6220-sysctrl34 then:35 required:36 - '#clock-cells'37 38properties:39 compatible:40 oneOf:41 - items:42 - enum:43 - hisilicon,sysctrl44 - hisilicon,hi6220-sysctrl45 - hisilicon,hi3519-sysctrl46 - const: syscon47 - items:48 - const: hisilicon,hip01-sysctrl49 - const: hisilicon,sysctrl50 51 reg:52 maxItems: 153 54 smp-offset:55 description: |56 offset in sysctrl for notifying slave cpu booting57 cpu 1, reg;58 cpu 2, reg + 0x4;59 cpu 3, reg + 0x8;60 If reg value is not zero, cpun exit wfi and go61 $ref: /schemas/types.yaml#/definitions/uint3262 63 resume-offset:64 description: offset in sysctrl for notifying cpu0 when resume65 $ref: /schemas/types.yaml#/definitions/uint3266 67 reboot-offset:68 description: offset in sysctrl for system reboot69 $ref: /schemas/types.yaml#/definitions/uint3270 71 '#clock-cells':72 const: 173 74 '#reset-cells':75 const: 176 77 '#address-cells':78 const: 179 80 '#size-cells':81 const: 182 83 ranges: true84 85patternProperties:86 '^clock@':87 type: object88 additionalProperties: false89 90 properties:91 compatible:92 enum:93 - hisilicon,hi3620-clock94 - hisilicon,hi3620-mmc-clock95 96 reg:97 maxItems: 198 99 '#clock-cells':100 const: 1101 102required:103 - compatible104 - reg105 106additionalProperties:107 type: object108 109examples:110 - |111 /* Hisilicon system controller */112 system-controller@802000 {113 compatible = "hisilicon,sysctrl", "syscon";114 #address-cells = <1>;115 #size-cells = <1>;116 ranges = <0 0x802000 0x1000>;117 reg = <0x802000 0x1000>;118 119 smp-offset = <0x31c>;120 resume-offset = <0x308>;121 reboot-offset = <0x4>;122 123 clock: clock@0 {124 compatible = "hisilicon,hi3620-clock";125 reg = <0 0x10000>;126 #clock-cells = <1>;127 };128 };129 130 /* HiP01 system controller */131 system-controller@10000000 {132 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";133 reg = <0x10000000 0x1000>;134 reboot-offset = <0x4>;135 };136 137 /* Hi6220 system controller */138 system-controller@f7030000 {139 compatible = "hisilicon,hi6220-sysctrl", "syscon";140 reg = <0xf7030000 0x2000>;141 #clock-cells = <1>;142 };143 144 /* Hi3519 system controller */145 system-controller@12010000 {146 compatible = "hisilicon,hi3519-sysctrl", "syscon";147 reg = <0x12010000 0x1000>;148 };149...150